Accelerating memory fault resolution by performing fast re-fetching

Patent metadata

Field	Value
Publication number	US-10402263-B2
Application number	US-201715831195-A
Country	US
Kind code	B2
Filing date	Dec 4, 2017
Priority date	Dec 4, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A method for handling load faults in an out-of-order processor is described. The method includes detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor; determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

First claim

What is claimed is:

1. A method for handling load faults in an out-of-order processor, the method comprising:
detecting, by a memory ordering buffer of the out-of-order processor, a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor;
determining, by the memory ordering buffer, whether instant reclamation is available for resolving the load fault of the load instruction; and
performing, in response to determining that instant reclamation is available for resolving the load fault of the load instruction, instant reclamation to re-fetch the load instruction for execution prior to attempting to retire the load instruction.

2. The method of claim 1 , wherein performing the instant reclamation comprises:
determining a branch instruction preceding the load instruction in program order; and
generating a reconstructed load address of the load instruction based on an address associated with the branch instruction and a set of address bits of the load instruction,
wherein the address associated with the branch instruction is one of the address of the branch instruction in memory and a target of the branch instruction.

3. The method of claim 2 , wherein generating the reconstructed load address of the load instruction comprises:
combining a set of upper bits of the branch address associated with the branch instruction with the set of address bits, such that the set of upper bits of the branch address associated with the branch instruction are upper bits of the reconstructed load address and the set of address bits are lower bits of the reconstructed load address.

4. The method of claim 2 , wherein performing the instant reclamation further comprises:
generating, by a reservation station, an early instant reclamation request based on one or more of a reorder buffer identifier, a store buffer identifier, and a load buffer identifier associated with the load instruction;
transmitting the early instant reclamation request to a jump execution unit;
detecting, by the jump execution unit in response to the early instant reclamation request, whether a mis-predicted branch instruction that occurs before the load instruction in program order is being handled by the out-of-order processor; and
transmitting, by the jump execution unit, a load clear to a front-end multiplexer to cause the front-end multiplexer to transmit the reconstructed load address, wherein re-fetching is performed starting from the reconstructed load address when the jump execution fails to detect a mis-predicted branch instruction that occurs before the load instruction in program order is being handled by the out-of-order processor.

5. The method of claim 4 , wherein the reorder buffer identifier, the store buffer identifier, and a load buffer identifier are stored within a load information table within one of the reservation station and the memory ordering buffer.

6. The method of claim 2 , wherein determining whether instant reclamation is available for resolving the load fault of the load instruction is based on a distance of the load instruction from the branch instruction preceding the load instruction in program order, and
wherein when the distance is less than a predetermined distance, the memory ordering buffer determines that instant reclamation is available for resolving the load fault of the load instruction.

7. The method of claim 1 , wherein the load fault is based on one of an external snoop hit, a memory disambiguation misprediction, and a memory renaming mismatch.

8. An instant reclamation system for an out-of-order processor, comprising:
a memory ordering buffer to detect a load fault corresponding to a load instruction that was executed out-of-order;
a reservation station to determine a branch instruction preceding the load instruction in program order; and
a front-end multiplexer to output a reconstructed load address of the load instruction based on an address associated with the branch instruction preceding the load instruction, wherein the reconstructed load address is to be used to re-fetch instructions, including the load instruction, for execution prior to attempting to retire the load instruction.

9. The instant reclamation system of claim 8 , wherein the address associated with the branch instruction is one of the address of the branch instruction in memory and a target of the branch instruction.

10. The instant reclamation system of claim 9 , wherein the instant reclamation system further comprises:
a combination unit to generate the reconstructed address of the load instruction based on the address associated with the branch instruction and a set of address bits of the load instruction,
wherein the combination unit generates the reconstructed address of the load instruction by combining a set of upper bits of the address associated with the branch instruction with the set of address bits, such that the set of upper bits of the address associated with the branch instruction are upper bits of the reconstructed address and the set of address bits are lower bits of the reconstructed load address and the load instruction is fetched for execution based on the reconstructed load address.

11. The instant reclamation system of claim 8 , further comprising:
a jump execution unit to:
detect whether a mis-predicted branch instruction that occurs before the load instruction in program order is being handled by the out-of-order processor, and
transmit a load clear to the front-end multiplexer to cause the front-end multiplexer to transmit the reconstructed load address, wherein re-fetching is performed starting from the reconstructed load address when the jump execution fails to detect a mis-predicted branch instruction that occurs before the load instruction in program order is being handled by the out-of-order processor.

12. The instant reclamation system of claim 11 , wherein the reservation station is to:
generate an early instant reclamation request based on one or more of a reorder buffer identifier, a store buffer identifier, and a load buffer identifier associated with the load instruction; and
transmit the early instant reclamation request to the jump execution unit such that the jump execution unit may detect whether a mis-predicted branch instruction that occurs before the load instruction in program order is being handled by the out-of-order processor.

13. The instant reclamation system of claim 12 , wherein the memory ordering buffer is to determine whether instant reclamation is permitted for resolving the load fault of the load instruction, wherein instant reclamation is permitted for the load instruction when a distance between the load instruction and a preceding branch instruction in program order is less than a predetermined distance.

14. The instant reclamation system of claim 8 , wherein the load fault is based on one of an external snoop hit, a memory disambiguation misprediction, and a memory renaming mismatch.

15. A non-transitory machine-readable medium containing instructions that, when performed by an out-of-order processor, cause the performance of operations comprising:
detecting a load fault corresponding to a load instruction that was executed out-of-order by the out-of-order processor;
determining whether instant reclamation is available for resolving the load fault of the load instruction; and
performing, in response to detecting determining that instant reclamation is available for resolving the load fault of the load instruction the load fault of the load instruction, instant reclamation to re-fetch and re-execute the load instruction f

Assignees

• Intel Corp

Inventors

• Sperber Zeev
• Shwartsman Stanislav
• Stark Iv Jared W
• Rappoport Lihu
• Yanover Igor
• Leifman George

Classifications

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F9/3865

  using deferred exception handling, e.g. exception flags · CPC title

• G06F9/3861 Primary

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3842

  Speculative instruction execution · CPC title