Instruction and logic for reducing data cache evictions in an out-of-order processor

Patent metadata

Field	Value
Publication number	US-9870209-B2
Application number	US-201414228697-A
Country	US
Kind code	B2
Filing date	Mar 28, 2014
Priority date	Mar 28, 2014
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A processor includes a resource scheduler, a dispatcher, and a memory execution unit. The memory execution unit includes logic to identify an executed, unretired store operation in a memory ordered buffer, determine that the store operation is speculative, determine whether an associated cache line in a data cache is non-speculative, and determine whether to block a write of the store operation results to the data cache based upon the determination that the store operation is speculative and a determination that the associated cache line is non-speculative.

First claim

What is claimed is:

1. A processor, comprising:
a resource scheduler including circuitry to assign alias resources to instructions within an atomic region of instructions, the atomic region including a plurality of reordered instructions; and
a memory execution unit including circuitry to:
identify an executed, unretired store operation from the atomic region in a memory ordered buffer;
determine that the store operation is speculative, wherein a speculative store operation is a store operation having a potential to cause a data-dependency violation;
determine that a particular cache line in a data cache associated with the store operation is non-speculative based on the particular cache line comprising result data of one or more non-speculative operations; and
determine that a write of a result of the store operation to the data cache is to be blocked, at least temporarily, based upon the determination that the store operation is speculative and a determination that the particular cache line is non-speculative.

2. The processor of claim 1 , wherein the memory execution unit further includes circuitry to:
determine that an exception to the determination that the write of the store operation result to the data cache is to be blocked is met;
evict the particular cache line to a write-back buffer; and
write the store operation result to the particular cache line.

3. The processor of claim 1 , wherein the memory execution unit further includes circuitry to:
determine whether an exception to the determination that the write of the store operation result to the data cache is to be blocked is met, including circuitry to:
determine whether the block of the write of the store operation result to the data cache would cause a block of a load operation; and

unblock the write of the store operation result to the data cache based upon a determination that the block of the write of the store operation result to the data cache would cause a block of a load operation.

4. The processor of claim 1 , wherein the memory execution unit further includes circuitry to:
determine whether an exception to the determination that the write of the store operation result to the data cache is to be blocked is met, including circuitry to:
determine whether the block of the write of the store operation result to the data cache would cause a block of a commit operation at retirement; and

unblock the write of the store operation result to the data cache based upon a determination that the block of the write of the store operation result to the data cache would cause a block of a commit operation at retirement.

5. The processor of claim 1 , wherein the memory execution unit further includes circuitry to predict whether a write of the store operation result will cause eviction of the particular cache line to the write-back-buffer.

6. The processor of claim 1 , wherein the memory execution unit further includes circuitry to:
determine whether a previous store operation caused eviction of the particular cache line to the write-back-buffer; and
predict whether the write of the store operation will cause eviction of the particular cache line to the write-back buffer, the prediction based upon the determination of whether a previous store operation caused eviction of the particular cache line to the write-back-buffer.

7. The processor of claim 1 , wherein the memory execution unit further includes circuitry to:
predict whether a write of the store operation will cause eviction of the particular cache line to the write-back-buffer; and
mark a younger store operation in the memory ordered buffer as associated with a speculative cache line.

8. A method comprising, within a processor:
dispatching an atomic region of instructions for execution;
identifying an executed, unretired store operation within the atomic region in a memory ordered buffer;
determining that the store operation is speculative, wherein a speculative store operation is a store operation having a potential to cause a data-dependency violation;
determining that a particular cache line in a data cache associated with the store operation is non-speculative based on the particular cache line comprising result data of one or more non-speculative operations; and
determining that a write of a result of the store operation to the data cache is to be blocked, at least temporarily, based upon the determination that the store operation is speculative and a determination that the particular cache line is non-speculative.

9. The method of claim 8 , further comprising:
determining whether an exception to the determination that the write of the store operation result to the data cache is to be blocked is met, including:
determining whether the block of the write of the store operation result to the data cache would cause a block of a load operation.

10. The method of claim 8 , further comprising:
determining whether an exception to the determination that the write of the store operation result to the data cache is to be blocked is met, including:
determining whether the block of the write of the store operation result to the data cache would cause a block of a commit operation at retirement.

11. The method of claim 8 , further comprising predicting whether a write of the store operation result will cause eviction of the particular cache line to the write-back-buffer.

12. The method of claim 8 , further comprising:
determining whether a previous store operation caused eviction of the particular cache line to the write-back-buffer; and
predicting whether the write of the store operation result will cause eviction of the particular cache line to the write-back buffer, the prediction based upon the determination whether the previous store operation caused eviction of the particular cache line to the write-back-buffer.

13. The method of claim 8 , further comprising:
predicting whether a write of the store operation result will cause eviction of the particular cache line to the write-back-buffer; and
marking a younger store operation in the memory ordered buffer as associated with a speculative cache line.

14. A system comprising a processor, the processor including:
a resource scheduler including circuitry to assign alias resources to instructions within an atomic region of instructions, the atomic region including a plurality of reordered instructions; and
a memory execution unit including circuitry to:
identify an executed, unretired store operation in the atomic region in a memory ordered buffer;
determine that the store operation is speculative, wherein a speculative store operation is a store operation having a potential to cause a data-dependency violation;
determine that a particular cache line in a data cache associated with the store operation is non-speculative based on the particular cache line comprising result data of one or more non-speculative operations; and
determine that a write of a result of the store operation to the data cache is to be blocked, at least temporarily, based upon the determination that the store operation is speculative and a determination that the particular cache line is non-speculative.

15. The system of claim 14 , wherein the memory execution unit further includes circuitry to:
determine that an exception to the determination that the write of the store operation result to the data cache is to be blocked is met;
evict the particular cache line to a write-back buffer; and
write the store operation result to the particular cache line.

16. The system of claim 14 , wherein the memory executio

Assignees

• Intel Corp

Inventors

• Kelm John H
• Pavlou Demos
• Hyuseinova Mirem

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F9/384

  Register renaming · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F9/3859

  Physics · mapped topic