Precise bottom junction formation for vertical transport field effect transistor with highly doped epitaxial source/drain, sharp junction gradient, and/or reduced parasitic capacitance

Patent metadata

Field	Value
Publication number	US-12068415-B2
Application number	US-202217966817-A
Country	US
Kind code	B2
Filing date	Oct 15, 2022
Priority date	Jun 15, 2020
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.

First claim

What is claimed is:

1. A structure comprising:
a substrate having a plurality of first lower source-drain regions and a plurality of second lower source-drain regions, the plurality of first lower source-drain regions being doped with one of an n-type dopant and a p-type dopant, the plurality of second lower source-drain regions being doped with an opposite one of the n-type dopant and the p-type dopant, the plurality of first lower source-drain regions and the plurality of second lower source-drain regions having coplanar outer surfaces, the plurality of second lower source-drain regions being integral with the substrate, the plurality of first lower source-drain regions being epitaxially grown material in cavities of the substrate;
wherein the plurality of first lower source-drain regions has a plurality of first bottom junctions integral with, and extending from, the outer surfaces of the plurality of first lower source-drain regions, the plurality of first bottom junctions being doped with the one of the n-type dopant and the p-type dopant;
wherein the plurality of second lower source-drain regions has a plurality of second bottom junctions extending from the outer surfaces of the plurality of second lower source-drain regions, the plurality of second bottom junctions being doped with the opposite one of the n-type dopant and the p-type dopant;
a plurality of first fins located on the plurality of first bottom junctions, the plurality of first fins having outer ends;
a plurality of second fins located on the plurality of second bottom junctions, and cooperatively with the plurality of first fins, defining intermediate cavities, the plurality of second fins having outer ends, the intermediate cavities extending into the plurality of first lower source-drain regions and the plurality of second lower source-drain regions;
a plurality of spacer-gate structures located in the intermediate cavities;
a plurality of first top junctions located on the outer ends of the plurality of first fins;
a plurality of second top junctions located on the outer ends of the plurality of second fins;
a plurality of first upper source-drain regions located outwardly of the plurality of spacer-gate structures in contact with the plurality of first top junctions, the plurality of first upper source-drain regions being doped with the one of the n-type dopant and the p-type dopant; and
a plurality of second upper source-drain regions located outwardly of the plurality of spacer-gate structures in contact with the plurality of second top junctions, the plurality of second upper source-drain regions being doped with the opposite one of the n-type dopant and the p-type dopant.

2. The structure of claim 1 , wherein the plurality of spacer-gate structures include lower spacers of dielectric material having a depth t s , and the plurality of first bottom junctions and the plurality of second bottom junctions respectively extend outward from the plurality of first source-drain regions and the plurality of second lower source-drain regions by a distance RIE, such that a lower junction-channel proximity x is given by x=t s −RIE.

3. The structure of claim 2 , wherein the plurality of spacer-gate structures further include gates outward of the lower spacers and upper spacers outward of the gates, the lower junction-channel proximity x being defined between outer surfaces of the plurality of first bottom junctions and the plurality of second bottom junctions and inner edges of the gates.

4. The structure of claim 3 , wherein the distance RIE ranges from about 6 nm to about 10 nm.

5. The structure of claim 3 , wherein the depth t s ranges from about 5 nm to about 20 nm.

6. The structure of claim 3 , wherein the depth t s ranges from about 5 nm to about 15 nm.

7. The structure of claim 3 , wherein the depth t s ranges from about 5 nm to about 12 nm.

8. The structure of claim 3 , wherein the depth t s ranges from about 9 nm to about 12 nm.

9. The structure of claim 3 , wherein the lower junction-channel proximity x ranges from about −3 nm to about 10 nm.

10. The structure of claim 1 , wherein the plurality of first lower source-drain regions has a dopant concentration of from about 1E19 to about 1E21 carriers per cubic centimeter.

11. The structure of claim 10 , wherein:
said one of an n-type dopant and a p-type dopant comprises the p-type dopant; and
said opposite one of the n-type dopant and the p-type dopant comprises the n-type dopant.

Assignees

• IBM

Inventors

• Zhao Kai
• Siddiqui Shahab
• Dechene Daniel James
• Krishnan Rishikesh
• Adams Charlotte Dewan

Classifications

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title