Storing sequential and random data in different layouts
US-12541327-B2 · Feb 3, 2026 · US
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Wu Jiangang patents
Wu Jiangang is listed as an inventor on 110 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Wu Jiangang |
| Total patents | 110 |
| First publication | Sep 10, 2020 |
| Latest publication | Feb 3, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Memory compaction management in memory devices
US-2025284589-A1 · Sep 11, 2025 · US
Performance control for a memory sub-system
US-2025231700-A1 · Jul 17, 2025 · US
Memory compaction management in memory devices
US-12332742-B2 · Jun 17, 2025 · US
Performance control for a memory sub-system
US-12314582-B2 · May 27, 2025 · US
Read counter for quality of service design
US-2025156123-A1 · May 15, 2025 · US
Automatic wordline status bypass management
US-12299304-B2 · May 13, 2025 · US
Storing sequential and random data in different layouts
US-2025110669-A1 · Apr 3, 2025 · US
Memory sub-system media management groups
US-2025103246-A1 · Mar 27, 2025 · US
Read counter for quality of service design
US-12229452-B2 · Feb 18, 2025 · US
Recent patents
Latest publications not already listed above.
Memory sub-system write sequence track
US-12182013-B2 · Dec 31, 2024 · US
Memory sub-system media management groups
US-12164804-B2 · Dec 10, 2024 · US
Memory sub-system scan
US-12148484-B2 · Nov 19, 2024 · US
Automatic wordline status bypass management
US-2024338138-A1 · Oct 10, 2024 · US
Voltage calibration scans to reduce memory device overhead
US-12057185-B2 · Aug 6, 2024 · US
Automatic wordline status bypass management
US-12026385-B2 · Jul 2, 2024 · US
Performance control for a memory sub-system
US-2024192866-A1 · Jun 13, 2024 · US
Full multi-plane operation enablement
US-12001340-B2 · Jun 4, 2024 · US
Memory compaction management in memory devices
US-2024176698-A1 · May 30, 2024 · US
Selective partitioning of sets of pages programmed to memory device
US-11995326-B2 · May 28, 2024 · US
Memory compaction management in memory devices
US-11934266-B2 · Mar 19, 2024 · US
Memory sub-system write sequence track
US-2024086316-A1 · Mar 14, 2024 · US
Managing voltage bin selection for blocks of a memory device
US-11928347-B2 · Mar 12, 2024 · US
Memory sub-system management based on dynamic control of wordline start voltage
US-11915785-B2 · Feb 27, 2024 · US
Performance control for a memory sub-system
US-11899948-B2 · Feb 13, 2024 · US
Managing workload of programming sets of pages to memory device
US-11886336-B2 · Jan 30, 2024 · US
Granular error reporting on multi-pass programming of non-volatile memory
US-11868202-B2 · Jan 9, 2024 · US
Memory sub-system logical block address remapping
US-11847051-B2 · Dec 19, 2023 · US
Memory sub-system management of firmware block record and device block record
US-11847065-B2 · Dec 19, 2023 · US
Memory sub-system write sequence track
US-11841794-B2 · Dec 12, 2023 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 110 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F3/0679 | 61 |
| G06F3/0659 | 53 |
| G06F12/0246 | 47 |
| G11C16/26 | 45 |
| G06F3/0604 | 41 |