Block family combination and voltage bin selection

Patent metadata

Field	Value
Publication number	US-11263134-B1
Application number	US-202017008024-A
Country	US
Kind code	B1
Filing date	Aug 31, 2020
Priority date	Aug 31, 2020
Publication date	Mar 1, 2022
Grant date	Mar 1, 2022

Abstract

A set of two or more block families associated with a first voltage bin are selected. Each block family includes two or more pages of a memory device that have been programmed within a corresponding time window. The set of two or more block families includes a first block family and a second block family. Values of a data state metric for each of the set of block families is determined. A first voltage for the first block family and a second voltage for the second block family is determined based on the values of the data state metric. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.

First claim

What is claimed is:

1. A method comprising:
selecting a plurality of block families associated with a first voltage bin, wherein each block family comprises a plurality of pages of a memory device that have been programmed within a corresponding time window, and wherein the plurality of block families comprises a first block family and a second block family;
determining values of a data state metric for each of the plurality of block families;
determining, based on the values of the data state metric, a first voltage for the first block family and a second voltage for the second block family; and
responsive to determining that a difference between the first voltage and the second voltage satisfies a block family combination criterion, merging the second block family with the first block family.

2. The method of claim 1 , wherein selecting the plurality of block families associated with the first voltage bin comprises:
accessing a block family metadata table comprising an entry for each block family of the memory device; and
identifying, by inspecting the block family metadata table, a bin boundary for the first voltage bin,
wherein the first block family of the plurality of block families is associated with the bin boundary of the first voltage bin and the second block family is temporally adjacent to the first block family.

3. The method of claim 1 , further comprising:
associating the merged first block family and the second block family with the first voltage bin or a second voltage bin based on the first voltage and the second voltage.

4. The method of claim 1 , wherein the plurality of block families further comprises a third block family, wherein the third block family is temporally adjacent to the first block family and the second block family.

5. The method of claim 1 , wherein determining the values of the data state metric for each of the plurality of block families comprises:
performing a series of read operations for a particular block family of the plurality of block families using a set of voltage offsets,
wherein a value of the data state metric for the particular block family corresponds to an error rate resulting from one or more of the series of read operations.

6. The method of claim 1 , wherein the difference between the first voltage and the second voltage satisfies the block family combination criterion responsive to exceeding a difference threshold value.

7. The method of claim 6 , further comprising:
responsive to determining that a number of unavailable block families associated with the first voltage bin exceeds a threshold number of unavailable block families, modifying the difference threshold value.

8. The method of claim 1 , wherein merging the second block family with the first block family comprises:
accessing a block metadata table comprising an entry for one or more pages of a memory device, wherein each entry comprises an indication of a particular block family associated with respective pages;
identifying, at the block metadata table, a first entry corresponding to the first block family and a second entry corresponding to the second block family;
updating the first entry to associate respective pages of the second block family with the first block family; and
erasing the second entry from the block metadata table.

9. The method of claim 8 , further comprising:
receiving a request to read data from respective pages of the second block family;
determine a threshold voltage offset associated with the second block family based on the updated first block entry of the block metadata table;
compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device; and
read, using the modified threshold voltage, data from a block of the second block family.

10. A system comprising:
a memory device; and
a processing device coupled to the memory device, the processing device to perform operations comprising:
determining values of a data state metric for each of a first plurality of block families associated with a first voltage bin, wherein each block family comprises a plurality of pages of a memory device that have been programmed within a corresponding time window, and wherein each measurement value corresponds to a state of data for a particular block family of the first plurality of block families;
responsive to determining, based on the values of the data state metric for each of the first plurality of block families, that a voltage for each of the first plurality of block families satisfies a block family combination criterion, merging each block family of the first plurality of block families;
responsive to determining that a continuation scan criterion is satisfied, selecting a second plurality of block families associated with the first voltage bin; and
performing a calibration scan for each block family of the second plurality of block families.

11. The system of claim 10 , wherein the processing device is to determine that the continuation scan criterion is satisfied responsive to:
associating the merged first plurality of block families with a second voltage bin based on a voltage shift for each of the first plurality of block families.

12. The system of claim 10 , wherein the processing device is to determine that the continuation scan criterion is satisfied responsive to:
determining that a number of unavailable block families at the memory device satisfies a threshold number.

13. The system of claim 10 , wherein to determine the values of the data state metric for each of the first plurality of block families, the processing device is to perform operations comprising:
performing a series of read operations for a particular block family of the first plurality of block families using a set of voltage offsets,
wherein a value of the data state metric for the particular block family corresponds to an error rate resulting from one or more of the series of read operations.

14. The system of claim 10 , wherein the processing device determines that the voltage for each of the first plurality of block families satisfies the block family combination criterion responsive to determining a difference between a first voltage for a first block family of the first plurality of block families and a second voltage for a second block family of the first plurality of block families exceeds a difference threshold value.

15. The system of claim 10 , wherein the first plurality of block families comprises a first block family and a second block family, wherein the first block family is associated with a bin boundary for the first voltage bin and the second block family is temporally adjacent to the first block family, and wherein a third block family of the second plurality of block families is temporally adjacent to the second block family.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
selecting a plurality of block families associated with a first voltage bin, wherein each block family comprises a plurality of pages of a memory device that have been programmed within a corresponding time window, and wherein the plurality of block families comprises a first block family and a second block family;
determining values of a data state metric for each of the plurality of block families;
determining, based on the values of the data state metric, a first voltage for the first block family and a second voltage for the second block family; a

Assignees

• Micron Technology Inc

Inventors

• Sheperek Michael
• Koudele Larry J
• Kaynak Mustafa N
• Nowell Shane

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F2212/7206

  Reconfiguration of flash memory system · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title