Power state aware scan frequency

Patent metadata

Field	Value
Publication number	US-11222704-B1
Application number	US-202017125902-A
Country	US
Kind code	B1
Filing date	Dec 17, 2020
Priority date	Dec 17, 2020
Publication date	Jan 11, 2022
Grant date	Jan 11, 2022

Abstract

A system can include a memory device and a processing device to perform operations that include performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with a scan frequency, and wherein each scan iteration comprises detecting a transition associated with the memory device from a first power state to a second power state, responsive to detecting the transition from the first power state to the second power state, determining an updated value of the scan frequency in view of the second power state, wherein one or more subsequent scan iterations are initiated in accordance with the updated value of the scan frequency, and performing one or more block family calibration operations.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled with the memory device, to perform operations comprising:
performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with a scan frequency, and wherein each scan iteration comprises:
detecting a transition associated with the memory device from a first power state to a second power state;
responsive to detecting the transition from the first power state to the second power state, determining an updated value of the scan frequency in view of the second power state, wherein one or more subsequent scan iterations are initiated in accordance with the updated value of the scan frequency; and
performing one or more block family calibration operations.

2. The system of claim 1 , wherein the second power state comprises an idle state, and the updated value of the scan frequency comprises a maximum scan frequency that corresponds to initiating scan iterations without delay between initiation of consecutive scan iterations.

3. The system of claim 1 , wherein the second power state comprises a hibernate state, wherein the updated value of the scan frequency comprises a threshold low power scan frequency, and wherein each iteration scans a number of pages of the memory device determined in view of a low power burst threshold criterion.

4. The system of claim 3 , wherein the operations further comprise:
requesting a wakeup notification at a time determined based on the scan frequency, wherein the wakeup notification corresponds to a wakeup from the hibernate state, and wherein each scan iteration is performed in response to the wakeup notification.

5. The system of claim 1 , wherein the second power state comprises a deep sleep state, and the operations further comprise:
sending, to the memory device, a request to defer the transition to the deep sleep state,
wherein the updated value of the scan frequency comprises a threshold maximum scan frequency; and
performing the block family calibration scan at the threshold maximum scan frequency for an amount of time determined in view of a threshold deferment scan time criterion.

6. The system of claim 1 , wherein the second power state comprises an active state, and the updated value of the scan comprises a predetermined active scan frequency.

7. The system of claim 1 , wherein performing one or more block family calibration operations comprises updating at least one bin pointer of at least one block family in view of a data state metric of at least one block of the at least one block family.

8. The system of claim 7 , wherein the at least one block family comprises an oldest block family of a plurality of block families associated with a first voltage bin, and updating at least one bin pointer of the at least one block family comprises:
identifying, according to a block family creation order, the oldest block family from the plurality of block families associated with the first voltage bin;
determining one or more values of the data state metric based on at least one block of the oldest block family;
identifying a second voltage bin in view of the values of the data state metric; and
associating the oldest block family with the second voltage bin.

9. The system of claim 1 , wherein one or more subsequent scan iterations are initiated in accordance with the updated value of the scan frequency.

10. A method comprising:
performing a block family calibration scan of a memory device, wherein the calibration scan comprises a first plurality of scan iterations and a second plurality of scan operations, wherein the first plurality of scan iterations are initiated in response to
determining that a memory device is in an idle power state;
performing a first plurality of scan iterations in accordance with a first scan frequency, wherein the first plurality of scan iterations comprise performing one or more first calibration operations for each block family of each voltage bin of the memory device;
detecting a transition associated with the memory device to a low power state; and
responsive to the transition to the low power state, performing a second plurality of scan iterations in accordance with a second scan frequency, wherein the second scan frequency is less than the first scan frequency, and
wherein the second plurality of scan iterations comprise requesting that the memory device perform one or more second calibration operations for at least one block family of at least one voltage bin of the memory device.

11. The method of claim 10 , wherein requesting that the memory device perform one or more second calibration operations for at least one block family of at least one voltage bin comprises requesting that the memory device perform the one or more second calibration operations in one or more bursts, wherein each burst comprises two or more calibration operations.

12. The method of claim 10 , further comprising:
detecting a transition associated with the memory device to an active power state;
responsive to the transition to the low power state:
determining a baseline scan frequency based on at least one of a workload intensity or a number of program-erase cycles, wherein the baseline scan frequency is less than the first scan frequency and greater than the second scan frequency;
performing a third plurality of scan iterations in accordance with the baseline scan frequency, wherein the third plurality of scan iterations comprise performing one or more third calibration operations for at least one block family of at least one voltage bin of the memory device.

13. The method of claim 12 , wherein the baseline scan frequency is based on a time between scans of two page lines.

14. The method of claim 12 , wherein the one or more third calibration operations for at least one block family of at least one voltage bin of the memory device are performed until the power state transitions to a different power state.

15. A non-transitory machine-readable storage medium storing instructions that cause a processing device to perform operations comprising:
performing a block family calibration scan of the memory device, wherein the calibration scan comprises a plurality of scan iterations, wherein each scan iteration is initiated in accordance with a scan frequency, and wherein each scan iteration comprises:
detecting a transition associated with the memory device from a first power state to a second power state;
responsive to detecting the transition from the first power state to the second power state, determining an updated value of the scan frequency in view of the second power state, wherein one or more subsequent scan iterations are initiated in accordance with the updated value of the scan frequency; and
performing one or more block family calibration operations.

16. The non-transitory machine-readable storage medium of claim 15 , wherein the second power state comprises an idle state, and the updated value of the scan frequency comprises a maximum scan frequency that corresponds to initiating scan iterations without delay between initiation of consecutive scan iterations.

17. The non-transitory machine-readable storage medium of claim 15 , wherein the second power state comprises a hibernate state, wherein the updated value of the scan frequency comprises a threshold low power scan frequency, and wherein each iteration scans a number of pages of the memory device determined in view of

Assignees

• Micron Technology Inc

Inventors

• Rayaprolu Vamsi Pavan

Classifications

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C2207/2227

  Standby or low power modes · CPC title