Stacked-layer board, electronic component module, and method of manufacturing stacked-layer board

Patent metadata

Field	Value
Publication number	US-12052821-B2
Application number	US-202217652104-A
Country	US
Kind code	B2
Filing date	Feb 23, 2022
Priority date	Oct 30, 2019
Publication date	Jul 30, 2024
Grant date	Jul 30, 2024

Abstract

A stacked-layer board includes a base material including a plurality of dielectric layers stacked on each other, a first main surface being a surface at one end in a stacking direction of the plurality of dielectric layers, and a second main surface being a surface at the other end in the stacking direction, and a first conductor provided on the first main surface, and a first groove is in a surface of the first conductor.

First claim

The invention claimed is:

1. A stacked-layer board comprising: a base material including: a plurality of dielectric layers stacked on each other; a first main surface being a surface at one end in a stacking direction of the plurality of dielectric layers; and a second main surface being a surface at another end in the stacking direction; a first conductor provided on the first main surface, wherein a first groove is in a surface of the first conductor; and a first base material groove provided in the first main surface; and a first land portion provided on the surface of the first conductor, wherein the first base material groove and the first conductor are formed at different positions on the first main surface, and wherein the first land portion extends beyond the surface of the first conductor only in a direction parallel to an extension direction of the first base material groove.

2. The stacked-layer board according to claim 1 , wherein the first groove has a shape crossing the surface of the first conductor.

3. The stacked-layer board according to claim 1 , wherein the first groove is provided in an entirety of the surface of the first conductor.

4. The stacked-layer board according to claim 1 , wherein the first conductor is a via conductor exposed from the first main surface.

5. The stacked-layer board according to claim 1 , further comprising a first electrode film provided on the surface of the first conductor.

6. The stacked-layer board according to claim 5 , wherein the first electrode film includes a depression having a shape corresponding to the first groove.

7. An electronic component module comprising:
the stacked-layer board according to claim 6 ; and
a first electronic component to be mounted on the first electrode film.

8. An electronic component module comprising:
the stacked-layer board according to claim 1 ;
a first electronic component to be mounted near the first main surface of the stacked-layer board; and
a first insulating resin layer covering the first main surface and the first electronic component.

9. The electronic component module according to claim 7 , further comprising:
a second conductor provided on the second main surface;
a second electrode film provided on a surface of the second conductor; and
a second electronic component to be mounted on the second electrode film.

10. The electronic component module according to claim 9 , wherein the second conductor is a via conductor exposed from the second main surface.

11. The electronic component module according to claim 9 , further comprising:
a second base material groove provided in the second main surface; and
a second insulating resin layer covering the second main surface and the second electronic component.

12. A method of manufacturing the stacked-layer board according to claim 1 , comprising:
a stacking step of stacking the plurality of dielectric layers interposed between restraint insulator layers;
a firing step of pressure-firing the plurality of dielectric layers interposed between the restraint insulator layers; and
a grinding step of grinding the pressure-fired restraint insulator layers and exposing the first main surface and the second main surface of the base material including the plurality of dielectric layers, wherein the grinding step performs the grinding so that a grinding mark may be generated in the surface of the first conductor provided on the first main surface of the base material.

13. The stacked-layer board according to claim 2 , wherein the first groove is provided in an entirety of the surface of the first conductor.

14. The stacked-layer board according to claim 2 , wherein the first conductor is a via conductor exposed from the first main surface.

15. The stacked-layer board according to claim 3 , wherein the first conductor is a via conductor exposed from the first main surface.

16. The stacked-layer board according to claim 1 , wherein the first base material groove is formed in a region of the first main surface that faces an electronic component mounted on the first main surface.

Assignees

• Murata Manufacturing Co

Inventors

• Goitsuka Takuya

Classifications

• H05K2201/09472

  Recessed pad for surface mounting; Recessed electrode of component · CPC title

• H05K1/113 Primary

  Via provided in pad; Pad over filled via · CPC title

• H05K3/4644

  by building the multilayer layer by layer, i.e. build-up multilayer circuits (making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602) · CPC title

• H05K2203/0392

  Pretreatment of metal, e.g. before finish plating, etching · CPC title

• H05K3/24

  Reinforcing of the conductive pattern {(by solder coating H05K3/3465)} · CPC title