Printed wiring board with bump and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2016100484-A1
Application number	US-201514874606-A
Country	US
Kind code	A1
Filing date	Oct 5, 2015
Priority date	Oct 3, 2014
Publication date	Apr 7, 2016
Grant date	—

Abstract

A printed wiring board includes a base insulating layer including an insulating material, a conductor layer formed on the base insulating layer and including conductor pads, a coating insulating layer formed on the base insulating layer such that the coating insulating layer is covering the conductor layer and having opening portions exposing the conductor pads, respectively, and bumps formed on the conductor pads respectively such that each of the bumps includes an electroless plating metal layer formed on a respective one of the conductor pads and a solder layer formed on the electroless plating metal layer, the electroless plating metal layer having an upper end surface formed such that a central portion of the upper end surface is recessed relative to a peripheral portion of the upper end surface.

First claim

What is claimed is:

1 . A printed wiring board, comprising:
a base insulating layer comprising an insulating material; a conductor layer formed on the base insulating layer and comprising a plurality of conductor pads; a coating insulating layer formed on the base insulating layer such that the coating insulating layer is covering the conductor layer and having a plurality of opening portions exposing the plurality of conductor pads, respectively; and a plurality of bumps formed on the plurality of conductor pads respectively such that each of the bumps comprises an electroless plating metal layer formed on a respective one of the conductor pads and a solder layer formed on the electroless plating metal layer, the electroless plating metal layer having an upper end surface formed such that a central portion of the upper end surface is recessed relative to a peripheral portion of the upper end surface.

2 . A printed wiring board according to claim 1 , wherein the electroless plating metal layer comprises an electroless nickel plating layer.

3 . A printed wiring board according to claim 2 , wherein the plurality of bumps is formed on the plurality of conductor pads respectively such that each of the bumps comprises an alloy layer interposed between the electroless plating metal layer and the solder layer.

4 . A printed wiring board according to claim 1 , wherein the coating insulating layer comprises a solder resist layer.

5 . A printed wiring board according to claim 1 , wherein the coating insulating layer comprises a resin film layer.

6 . A printed wiring board according to claim 1 , wherein the solder layer is formed on the electroless plating metal layer such that the solder layer is not extending over a surface of the coating insulating layer.

7 . A printed wiring board according to claim 1 , wherein the electroless plating metal layer has an upper end portion projecting with respect to a surface of the coating insulating layer such that the upper end portion has a diameter which is greater than an upper edge of a respective one of the opening portions, and the solder layer has a diameter which is greater than the upper edge of the respective one of the opening portions.

8 . A printed wiring board according to claim 1 , wherein the plurality of opening portions is formed in the coating insulating layer at a pitch such that each of the opening portions has a diameter which is one half of the pitch or less.

9 . A printed wiring board according to claim 1 , wherein the plurality of opening portions is formed in the coating insulating layer at a pitch in a range of 30 μm to 60 μm.

10 . A printed wiring board according to claim 1 , wherein the electroless plating metal layer is made of an electroless nickel plating layer.

11 . A printed wiring board according to claim 10 , wherein the plurality of bumps is formed on the plurality of conductor pads respectively such that each of the bumps comprises an alloy layer interposed between the electroless plating metal layer and the solder layer.

12 . A printed wiring board according to claim 2 , wherein the coating insulating layer comprises a solder resist layer.

13 . A printed wiring board according to claim 2 , wherein the coating insulating layer comprises a resin film layer.

14 . A printed wiring board according to claim 2 , wherein the solder layer is formed on the electroless plating metal layer such that the solder layer is not extending over a surface of the coating insulating layer.

15 . A printed wiring board according to claim 2 , wherein the electroless plating metal layer has an upper end portion projecting with respect to a surface of the coating insulating layer such that the upper end portion has a diameter which is greater than an upper edge of a respective one of the opening portions, and the solder layer has a diameter which is greater than the upper edge of the respective one of the opening portions.

16 . A printed wiring board according to claim 2 , wherein the plurality of opening portions is formed in the coating insulating layer at a pitch such that each of the opening portions has a diameter which is one half of the pitch or less.

17 . A printed wiring board according to claim 2 , wherein the plurality of opening portions is formed in the coating insulating layer at a pitch in a range of 30 μm to 60 μm.

18 . A method for manufacturing a printed wiring board, comprising:
preparing a printed wiring board comprising a base insulating layer comprising an insulating material, a conductor layer formed on the base insulating layer and comprising a plurality of conductor pads, and a coating insulating layer formed on the base insulating layer such that the coating insulating layer is covering the conductor layer; forming a plurality of opening portions penetrating through the coating insulating layer such that the plurality of opening portions reaches the plurality of conductor pads, respectively; forming in each of the opening portions an electroless plating metal layer such that the electroless plating metal layer connects to a respective one of the conductor pads and has an upper end surface having a central portion which is recessed relative to a peripheral portion of the upper end surface; mounting solder only on the upper end surface of the electroless plating metal layer through an adhesive layer; and reflowing the solder by applying heat such that a solder layer is formed on the upper end surface of the electroless plating metal layer and a bump comprising the electroless plating metal layer and the solder layer protruding from a surface of the coating insulating layer is formed.

19 . A method for manufacturing a printed wiring board according to claim 18 , wherein the forming of the electroless plating metal layer comprises forming an electroless nickel plating layer.

20 . A method for manufacturing a printed wiring board according to claim 19 , wherein the reflowing of the solder comprises reflowing the solder such that an alloy layer is formed between the electroless nickel plating layer and the solder layer.

Assignees

• Ibiden Co Ltd

Inventors

• Kunieda Masatoshi
• Tanno Katsuhiko

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title