Programmable address mapping and memory access operations

Patent metadata

Field	Value
Publication number	US-2016019161-A1
Application number	US-201314773549-A
Country	US
Kind code	A1
Filing date	Mar 12, 2013
Priority date	Mar 12, 2013
Publication date	Jan 21, 2016
Grant date	—

Abstract

Programmable address mapping and memory access operations are disclosed. An example apparatus includes an address translator to translate a first host physical address to a first intermediate address. The example apparatus also includes a programmable address decoder to decode the first intermediate address to a first hardware memory address of a first addressable memory location in a memory, the programmable address decoder to receive a first command to associate the first host physical address with a second addressable memory location in the memory by changing a mapping between the first intermediate address and a second hardware memory address of the second addressable memory location.

First claim

What is claimed is:

1 . An apparatus comprising:
an address translator to translate a first host physical address to a first intermediate address; and a programmable address decoder to decode the first intermediate address to a first hardware memory address of a first addressable memory location in a memory, the programmable address decoder to receive a first command to associate the first host physical address with a second addressable memory location in the memory by changing a mapping between the first intermediate address and a second hardware memory address of the second addressable memory location.

2 . The apparatus of claim 1 , wherein the address translator is to translate a second host physical address to a second intermediate address, and the programmable address decoder is to decode the second intermediate address to a third hardware memory address of a third addressable memory location in the memory, the programmable address decoder to receive a second command to associate the second host physical address with the first addressable memory location by changing a mapping between the second intermediate address and the first hardware memory address.

3 . The apparatus as defined in claim 1 , wherein the first addressable memory location is one of a plurality of addressable memory locations that form an array of addressable memory locations, each addressable memory location of the array of addressable memory locations has a different hardware memory address, each of the plurality of addressable memory locations being associated with a corresponding intermediate address, the programmable address decoder to decode the intermediate addresses to corresponding hardware memory addresses of the addressable memory locations; and
the programmable address decoder to receive a second command to change a mapping between the intermediate address and the hardware memory addresses to re-map the intermediate addresses with different ones of the plurality of addressable memory locations.

4 . The apparatus as defined in claim 3 , further comprising an address modifier to change mappings between the intermediate addresses and the hardware memory addresses of the addressable memory locations.

5 . The apparatus as defined in claim 1 , wherein the address translator is to translate a second host physical address to a second intermediate address, the programmable address decoder to receive a second command to write a data value to the first addressable memory location, and further comprising an address modifier to associate the second host physical address with the first addressable memory location by mapping the second intermediate address to the first hardware memory address of the first addressable memory location.

6 . A method comprising:
translating a first host physical address to a first intermediate address; decoding the first intermediate address to a first secondary physical address; decoding the first secondary physical address to a hardware memory address of a first addressable memory location in a memory; and receiving a first command to associate the first host physical address with a second addressable memory location in the memory by changing a mapping between the first intermediate address and a second secondary physical address that decodes to a second hardware memory address of the second addressable memory location.

7 . The method of claim 6 , further comprising:
translating a second host physical address to a second intermediate address; decoding the second intermediate address to a third secondary physical address that decodes to a third hardware memory address of a third addressable memory location in the memory; and receiving a second command to associate the second host physical address with the first secondary physical address by changing a mapping of the second intermediate address to the first secondary physical address.

8 . The method of claim 6 , wherein the first addressable memory location is one of a plurality of addressable memory locations that form an array of addressable memory locations, each addressable memory location of the array of addressable memory locations having a different hardware memory address;
each of the hardware memory addresses associated with a secondary physical address, wherein each of the secondary physical addresses decodes to one of the hardware memory addresses; each of the secondary physical addresses being associated with an intermediate address, wherein each of the intermediate addresses decodes to one of the secondary physical addresses; and further comprising receiving a second command to change a mapping between the intermediate addresses and the plurality of addressable memory locations to associate the intermediate addresses with different ones of the secondary physical addresses, each of the secondary physical addresses being associated with one of the plurality of addressable memory locations of the array of addressable memory locations.

9 . The method of claim 8 , further comprising changing the order of the intermediate addresses relative to the order of the secondary physical addresses that are associated with the intermediate addresses.

10 . The method of claim 6 , further comprising translating a second host physical address to a second intermediate address; and
receiving a second command to write a data value to the first addressable memory location and to associate the second host physical address with the first addressable memory location by changing a mapping between the second intermediate address and the first secondary physical address.

11 . A tangible machine readable storage medium comprising instructions that, when executed, cause a machine to at least:
translate a first host physical address to a first intermediate address; decode the first intermediate address to a first hardware memory address of a first addressable memory location in a memory; and associate the first host physical address with a second addressable memory location in the memory in response to a first command by changing a mapping between the first intermediate address and a second hardware memory address of the second addressable memory location.

12 . The storage medium as defined in claim 11 , wherein the instructions, when executed, cause the machine to:
translate a second host physical address to a second intermediate address; decode the second intermediate address to a third hardware memory address of a third addressable memory location in the memory; and receive a second command to associate the second host physical address with the first addressable memory location by changing a mapping of the second intermediate address to the first hardware memory address.

13 . The storage medium as defined in claim 11 , wherein the first addressable memory location is one of a plurality of addressable memory locations that form an array of addressable memory locations, each addressable memory location of the array of addressable memory locations having a different hardware memory address;
each of the plurality of addressable memory locations being associated with a corresponding intermediate address, wherein each of the intermediate addresses decodes to one of the addressable memory locations; and when executed, the instructions further cause the machine to change a mapping between the intermediate address and the hardware memory address in response to a second command to re-map the intermediate addresses with different ones of the plurality of addressable memory locations.

14 . The storage medium as defined in claim 13 , wherein the instructions, when execu

Assignees

• Hewlett Packard Development Co

Inventors

• Patel Tushar
• Kelly Terence P
• Wright Mitchel E

Classifications

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title

• G06F2212/305

  being part of a memory device, e.g. cache DRAM · CPC title

• G06F12/1036 Primary

  for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence) · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title