Methods and systems for implementing stream data updates
US-2026079648-A1 · Mar 19, 2026 · US
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Subbarao Sanjay patents
Subbarao Sanjay is listed as an inventor on 120 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Subbarao Sanjay |
| Total patents | 120 |
| First publication | Oct 20, 2016 |
| Latest publication | Mar 19, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Methods and systems for implementing stream data updates
US-12498885-B2 · Dec 16, 2025 · US
Buffer allocation for reducing block transit penalty
US-12498886-B2 · Dec 16, 2025 · US
Multiple-pass programming of memory cells using temporary parity generation
US-12481463-B2 · Nov 25, 2025 · US
Methods and systems for implementing stream data updates
US-2025165182-A1 · May 22, 2025 · US
Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system
US-2025165403-A1 · May 22, 2025 · US
Block failure protection for zone memory system
US-2025138944-A1 · May 1, 2025 · US
Block failure protection for zone memory system
US-12216541-B2 · Feb 4, 2025 · US
Caching of logical-to-physical mapping information in a memory sub-system
US-2025021488-A1 · Jan 16, 2025 · US
Storing a logical-to-physical mapping in nand memory
US-2025013579-A1 · Jan 9, 2025 · US
Recent patents
Latest publications not already listed above.
Buffer allocation for reducing block transit penalty
US-2024393980-A1 · Nov 28, 2024 · US
Multi-Pass Data Programming in a Memory Sub-System having Multiple Dies and Planes
US-2024377991-A1 · Nov 14, 2024 · US
Timed data transfer between a host system and a memory sub-system
US-2024370373-A1 · Nov 7, 2024 · US
Caching of logical-to-physical mapping information in a memory sub-system
US-12130748-B2 · Oct 29, 2024 · US
Storing a logical-to-physical mapping in NAND memory
US-12124380-B2 · Oct 22, 2024 · US
Memory block programming using defectivity information
US-2024347128-A1 · Oct 17, 2024 · US
Multiple-pass programming of memory cells using temporary parity generation
US-2024302999-A1 · Sep 12, 2024 · US
Buffer allocation for reducing block transit penalty
US-12079517-B2 · Sep 3, 2024 · US
Memory block programming using defectivity information
US-12051479-B2 · Jul 30, 2024 · US
Multi-pass data programming in a memory sub-system having multiple dies and planes
US-12050809-B2 · Jul 30, 2024 · US
Timed data transfer between a host system and a memory sub-system
US-12045168-B2 · Jul 23, 2024 · US
Multiple-pass programming of memory cells using temporary parity generation
US-12001721-B2 · Jun 4, 2024 · US
Block failure protection for zone memory system
US-2024152424-A1 · May 9, 2024 · US
Just-in-time (jit) scheduler for memory subsystems
US-2024078199-A1 · Mar 7, 2024 · US
Virtual management unit scheme for two-pass programming in a memory sub-system
US-11922011-B2 · Mar 5, 2024 · US
Block failure protection for zone memory system
US-2024070020-A1 · Feb 29, 2024 · US
Block failure protection for zone memory system
US-11914471-B1 · Feb 27, 2024 · US
Multiple-pass programming of memory cells using temporary parity generation
US-2024045616-A1 · Feb 8, 2024 · US
Management of Programming Mode Transitions to Accommodate a Constant Size of Data Transfer between a Host System and a Memory Sub-System
US-2024037039-A1 · Feb 1, 2024 · US
Partial Execution of a Write Command from a Host System
US-2024036768-A1 · Feb 1, 2024 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Micron Technology Inc | 78 |
| Western Digital Tech Inc | 37 |
| HGST Netherlands BV | 4 |
| Sk Hynix Nand Product Solutions Corp Dba Solidigm | 2 |
| Sk Hynix Nand Product Solutions Corp | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F12/0246 | 60 |
| G06F3/0679 | 57 |
| G06F3/0659 | 53 |
| G06F2212/7201 | 53 |
| G06F3/064 | 40 |