Method of manufacturing an integrated circuit device

Patent metadata

Field	Value
Publication number	US-12040326-B2
Application number	US-202318212304-A
Country	US
Kind code	B2
Filing date	Jun 21, 2023
Priority date	Dec 2, 2020
Publication date	Jul 16, 2024
Grant date	Jul 16, 2024

Abstract

An integrated circuit device including a substrate including first and second device regions; a first fin active region on the first device region; a second fin active region on the second device region; an isolation film covering side walls of the active regions; gate cut insulating patterns on the isolation film on the device regions; a gate line extending on the fin active regions, the gate line having a length limited by the gate cut insulating patterns; and an inter-region insulating pattern on the isolation film between the fin active regions and at least partially penetrating the gate line in a vertical direction, wherein the inter-region insulating pattern has a bottom surface proximate to the substrate, a top surface distal to the substrate, and a side wall linearly extending from the bottom to the top surface.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit device, the method comprising:
forming a plurality of fin active regions extending lengthwise in a first horizontal direction on a substrate;
forming an isolation film on the substrate, the isolation film covering both side walls of each of the plurality of fin active regions;
forming a dummy gate layer over the plurality of fin active regions and the isolation film, the dummy gate layer extending on the plurality of fin active regions in a second horizontal direction that crosses the first horizontal direction;
forming a plurality of gate cut spaces by etching portions of the dummy gate layer to expose the isolation film through the plurality of gate cut spaces, each of the plurality of gate cut spaces extending lengthwise in the first horizontal direction;
forming a plurality of gate cut insulating films respectively filling the plurality of gate cut spaces;
forming an inter-region insulating pattern from a selected gate cut insulating film from among the plurality of gate cut insulating films by replacing a portion of the selected gate cut insulating film with a sacrificial film, a height of the inter-region insulating pattern in a vertical direction being less than a height of each of the plurality of gate cut insulating films in the vertical direction;
forming a plurality of gate spaces by removing the dummy gate layer, the plurality of gate spaces including a first gate space and a second gate space separated by the inter-region insulating pattern;
forming a gate dielectric film which conformally covers each of the plurality of fin active regions, the plurality of gate cut insulating films, the inter-region insulating pattern, and the sacrificial film in the plurality of gate spaces;
exposing a top surface of the inter-region insulating pattern by removing the sacrificial film; and
forming a gate line in the first gate space and the second gate space, the gate line including a gate connecting portion covering the top surface of the inter-region insulating pattern.

2. The method of claim 1 , wherein:
the plurality of fin active regions includes a first fin active region on a first device region of the substrate, and a second fin active region on a second device region of the substrate, and
the selected gate cut insulating film is between the first fin active region and the second fin active region.

3. The method of claim 1 , wherein the sacrificial film includes a material, which has an etch selectivity with respect to a material of the dummy gate layer.

4. The method of claim 1 , wherein the dummy gate layer includes polysilicon, the plurality of gate cut insulating films include silicon nitride, and the sacrificial film includes silicon oxide.

5. The method of claim 1 , wherein:
the plurality of fin active regions includes a first fin active region on a first device region of the substrate, and a second fin active region on a second device region of the substrate, and
a first shortest distance in the second horizontal direction between the inter-region insulating pattern and the first fin active region is the same as a second shortest distance in the second horizontal direction between the inter-region insulating pattern and the second fin active region.

6. The method of claim 1 , wherein:
the plurality of fin active regions includes a first fin active region on a first device region of the substrate, and a second fin active region on a second device region of the substrate, and
a first shortest distance in the second horizontal direction between the inter-region insulating pattern and the first fin active region is different from a second shortest distance in the second horizontal direction between the inter-region insulating pattern and the second fin active region.

7. The method of claim 1 , wherein in the forming of the inter-region insulating pattern, the inter-region insulating pattern is formed to have a non-planar top surface.

8. The method of claim 1 , wherein:
the plurality of fin active regions includes a first fin active region on a first device region of the substrate, and a second fin active region on a second device region of the substrate, and
forming the gate line includes:
forming a first gate portion of the gate line covering the first fin active region on the first device region and having a first stack structure,
forming a second gate portion of the gate line covering the second fin active region on the second device region and having a second stack structure that is different from the first stack structure, the first gate portion being separated from the second gate portion with the inter-region insulating pattern between the first gate portion and the second gate portion in the second horizontal direction, and
forming the gate connecting portion integrally connected to the first gate portion and the second gate portion, the gate connecting portion having a structure different from each of the first stack structure and the second stack structure.

9. The method of claim 1 , wherein:
the plurality of fin active regions includes a first fin active region on a first device region of the substrate, and a second fin active region on a second device region of the substrate, and
forming the gate line includes:
forming a first conductive layer covering the first fin active region and partially filling the first gate space before the exposing of the top surface of the inter-region insulating pattern,
forming a second conductive layer covering the second fin active region and partially filling the second gate space before the exposing of the top surface of the inter-region insulating pattern and after the forming of the first conductive layer, and
forming a gap-fill metal film on the first conductive layer, the second conductive layer, and the inter-region insulating pattern.

10. The method of claim 9 , wherein forming the gate line further includes planarizing the gap-fill metal film, the first conductive layer, and the second conductive layer to expose a topmost surface of each of the plurality of gate cut insulating films other than the selected gate cut insulating film.

11. A method of manufacturing an integrated circuit device, the method comprising:
forming a structure on a substrate, the structure including a pair of fin active regions and a pair of nanosheet stacks on the pair of fin active regions, the pair of fin active regions extending lengthwise in a first horizontal direction, each of the pair of nanosheet stacks including a plurality of nanosheets which overlap each other in a vertical direction;
forming an isolation film on the substrate, the isolation film covering both side walls of each of the pair of fin active regions;
forming a dummy gate layer over the pair of nanosheet stacks and the isolation film, the dummy gate layer extending lengthwise in a second horizontal direction that crosses the first horizontal direction;
forming a plurality of gate cut spaces by etching portions of the dummy gate layer to expose the isolation film through the plurality of gate cut spaces, each of the plurality of gate cut spaces extending lengthwise in the first horizontal direction to cross the dummy gate layer, the plurality of gate cut spaces including a first space interposed between the pair of nanosheet stacks, a second space spaced apart from the first space with a first nanosheet stack selected from among the pair of nanosheet stacks between the first and second spaces, and a third space spaced apart from the first space with a second nanosheet stack selected from among the pair of nanosheet stacks between the first and third spaces;
forming a plurality of gate cut

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang Junggil
• Kim Minju
• Koh Donghyi

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title