Semiconductor device and method of forming the semiconductor device

Patent metadata

Field	Value
Publication number	US-9947664-B1
Application number	US-201615294467-A
Country	US
Kind code	B1
Filing date	Oct 14, 2016
Priority date	Oct 14, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A semiconductor device includes a first vertical field effect transistor (VFET) formed on a substrate, and including a first fin and a first gate formed on the first fin, a second VFET formed on the substrate and connected in parallel with the first VFET, and including a second fin and a second gate formed on the second fin, a third VFET formed on the substrate and including a third fin, the first and second gates being formed on the third fin, and a fourth VFET formed on the substrate and connected in series with the third VFET, and including a fourth fin, the first and second gates being formed on the fourth fin.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first vertical field effect transistor (VFET) formed on a substrate, and comprising a first fin and a first gate formed on the first fin;
a second VFET formed on the substrate and connected in parallel with the first VFET, and comprising a second fin and a second gate formed on the second fin;
a third VFET formed on the substrate and comprising a third fin, the first and second gates being formed on the third fin; and
a fourth VFET formed on the substrate and connected in series with the third VFET, and comprising a fourth fin, the first and second gates being formed on the fourth fin.

2. The semiconductor device of claim 1 , wherein the first and second VFETs comprise p-type VFETs and the third and fourth VFETs comprises n-type VFETs, and the semiconductor device comprises a complementary metal oxide semiconductor (CMOS) NAND device.

3. The semiconductor device of claim 2 , wherein the first and second VFETs are formed on an p-type substrate, and the third and fourth VFETs are formed on a n-type substrate, and
wherein the device further comprises:
a V DD contact formed on the p-type substrate; and
a ground contact formed on the n-type substrate.

4. The semiconductor device of claim 1 , wherein the first and second VFETs comprise n-type VFETs and the third and fourth VFETs comprises p-type VFETs, and the semiconductor device comprises a complementary metal oxide semiconductor (CMOS) NOR device.

5. The semiconductor device of claim 4 , wherein the first and second VFETs are formed on an n-type substrate, and the third and fourth VFETs are formed on a p-type substrate, and
wherein the device further comprises:
a V DD contact formed on the n-type substrate; and
a ground contact formed on the p-type substrate.

6. The semiconductor device of claim 1 , wherein the second p-type VFET is formed adjacent to the first p-type VFET in a first direction, and the second n-type VFET is formed adjacent to the first n-type VFET in the first direction.

7. The semiconductor device of claim 6 , wherein the first n-type VFET is formed adjacent to the first p-type in a second direction perpendicular to the first direction, and the second n-type VFET is formed adjacent to the second p-type FET in the second direction.

8. The semiconductor device of claim 1 , wherein the first gate is formed on the third fin of the third VFET under the second gate.

9. The semiconductor device of claim 8 , wherein the third fin of the third VFET comprises an undoped region between the first and second gates, and the undoped region is gated by a fringing effect which couples the first and second gates.

10. The semiconductor device of claim 9 , wherein a distance between the first and second gates on the third fin is in a range from 1 nm to 4 nm.

11. The semiconductor device of claim 1 , wherein the first gate is formed on the fourth fin of the fourth VFET under the second gate.

12. The semiconductor device of claim 11 , wherein the fourth fin of the fourth VFET comprises an undoped region between the first and second gates, and the undoped region is gated by a fringing effect which couples the first and second gates.

13. The semiconductor device of claim 12 , wherein a distance between the first and second gates on the fourth fin is in a range from 1 nm to 4 nm.

14. The semiconductor device of claim 1 , wherein the first gate comprises a first width on the first fin and a second width on the third and fourth fins, the first width being greater than the second width, and
wherein the second gate comprises a first width on the second fin and a second width on the third and fourth fins, the first width of the second gate being greater than the second width of the second gate.

15. The semiconductor device of claim 1 , further comprising:
a device-bus interconnect formed between the first and second fins, and the third and fourth fins.

16. The semiconductor device of claim 15 , where the device-bus interconnect comprises an inversion layer.

17. The semiconductor device of claim 15 , where the device-bus interconnect comprises a doped portion of the first, second, third and fourth fins.

18. The semiconductor device of claim 15 , wherein the device-bus interconnect comprises a contact formed between the first and second fins, and the third and fourth fins.

19. A method of forming a semiconductor device comprising:
forming a first vertical field effect transistor (VFET) on a substrate, the first VFET comprising a first fin and a first gate formed on the first fin;
forming a second VFET on the substrate, the second VFET being connected in parallel with the first VFET, and comprising a second fin and a second gate formed on the second fin;
forming a third VFET on the substrate, the third VFET comprising a third fin, and the first and second gates being formed on the third fin; and
forming a fourth VFET on the substrate, the fourth VFET being connected in series with the third VFET, and comprising a fourth fin, the first and second gates being formed on the fourth fin.

Assignees

• IBM

Inventors

• Anderson Brent Alan
• Fetterolf Shawn P
• Hook Terence B

Classifications

• H10W90/00

  Package configurations · CPC title

• H01L21/823431

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L21/823487

  Electricity · mapped topic

• H01L27/0924 Primary

  Electricity · mapped topic