Three-dimensional memory devices having through stair contacts and methods for forming the same

Patent metadata

Field	Value
Publication number	US-12035530-B2
Application number	US-202318374507-A
Country	US
Kind code	B2
Filing date	Sep 28, 2023
Priority date	Jan 2, 2019
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

In an example, a three-dimensional (3D) memory device includes a memory stack and a through stair contact (TSC). The memory stack includes interleaved conductive layers and dielectric layers. The memory stack includes stairs in a staircase region. The TSC extends through the memory stack in the staircase region. The TSC includes a first conductor layer and a first spacer circumscribing the first conductor layer. The first conductor layer of the TSC is insulated from the conductive layers of the memory stack by the first spacer.

First claim

What is claimed is:

1. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers, wherein the memory stack comprises stairs in a staircase region; and
a through stair contact (TSC) extending through the memory stack in the staircase region, wherein the TSC comprises a first conductor layer and a first spacer circumscribing the first conductor layer, and the first conductor layer of the TSC is insulated from the conductive layers of the memory stack by the first spacer.

2. The 3D memory device of claim 1 , wherein the first spacer comprises a dielectric material.

3. The 3D memory device of claim 1 , further comprising a channel structure extending through the memory stack in a core array region adjacent to the staircase region.

4. The 3D memory device of claim 3 , wherein the TSC extends vertically through a smaller number of the conductive layers and dielectric layers of the memory stack than the channel structure.

5. The 3D memory device of claim 1 , further comprising a first substrate on which the memory stack is formed.

6. The 3D memory device of claim 5 , wherein the first substrate comprises silicon, and the TSC is in contact with the first substrate.

7. The 3D memory device of claim 1 , further comprising a peripheral contact outside of the memory stack, wherein the peripheral contact comprises a second conductor layer and a second spacer circumscribing the second conductor layer.

8. The 3D memory device of claim 1 , further comprising a word line contact in contact with one of the conductive layers of the memory stack in the staircase region.

9. The 3D memory device of claim 8 , wherein a cross-section of the word line contact and a cross-section of the TSC have a same shape.

10. The 3D memory device of claim 1 , wherein a cross-section of the TSC has a circular shape.

11. The 3D memory device of claim 1 , further comprising a peripheral device above or below the memory stack.

12. The 3D memory device of claim 11 , further comprising a second substrate on which the peripheral device is formed.

13. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers;
a channel structure extending through the memory stack in a first region; and
a through stair contact (TSC) extending through the memory stack in a second region different from the first region, wherein the TSC extends through a smaller number of the conductive layers and dielectric layers of the memory stack than the channel structure, and the TSC comprises a conductor layer and a spacer laterally surrounding the conductor layer.

14. The 3D memory device of claim 13 , further comprising a word line contact in contact with one of the conductive layers of the memory stack in the first region.

15. The 3D memory device of claim 14 , wherein a lateral dimension of the word line contact is less than a lateral dimension of the conductor layer of the TSC.

16. The 3D memory device of claim 14 , wherein the word line contact and the conductor layer of the TSC comprise a same conductive material.

17. A three-dimensional (3D) memory device, comprising:
a memory stack comprising interleaved conductive layers and dielectric layers, wherein the memory stack comprises stairs in a staircase region;
a word line contact in contact with one of the conductive layers of the memory stack in the staircase region; and
a through stair contact (TSC) extending through the memory stack in the staircase region, wherein the TSC and the word line contact each comprise a conductor layer having a same material.

18. The 3D memory device of claim 17 , wherein the TSC further comprises a spacer circumscribing the conductor layer, and the conductor layer of the TSC is insulated from the conductive layers of the memory stack by the spacer.

19. The 3D memory device of claim 17 , further comprising a channel structure extending through the memory stack in a core array region adjacent to the staircase region.

20. The 3D memory device of claim 17 , further comprising a substrate on which the memory stack is formed, and the TSC is in contact with the substrate.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wei Qinxiang
• Sun Jianhua
• Xia Ji

Classifications

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title