Word line contact regions for three-dimensional non-volatile memory

Patent metadata

Field	Value
Publication number	US-10115440-B2
Application number	US-201715625848-A
Country	US
Kind code	B2
Filing date	Jun 16, 2017
Priority date	Jan 10, 2017
Publication date	Oct 30, 2018
Grant date	Oct 30, 2018

Abstract

Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.

First claim

What is claimed is:

1. An apparatus comprising:
a stack of word line layers comprising word lines for a three-dimensional non-volatile memory array, the stack of word line layers comprising a plurality of tiers;
a plurality of word line switch transistors for transferring word line bias voltages to the word lines;
a plurality of word line contact regions for coupling the word line switch transistors to the word lines, a word line contact region comprising a stepped structure for a tier of the word line layers, wherein a level region separates a word line contact region for a first tier from a word line contact region for a second tier; and
a plurality of connectors coupling the word line switch transistors to the word lines, the connectors comprising vertical conductors, wherein connectors for a single word line contact region comprise vertical conductors disposed within the single word line contact region, at a first side of the single word line contact region, and at a second side of the single word line contact region.

2. The apparatus of claim 1 , wherein a tier comprises a set of consecutive word line layers.

3. The apparatus of claim 1 , wherein a word line switch transistor region comprising the word line switch transistors is disposed under the word line contact regions.

4. The apparatus of claim 3 , further comprising further vertical conductors for communication between the three-dimensional non-volatile memory array and a plurality of transistors for the array, wherein the vertical conductors are disposed above the word line switch transistor region.

5. The apparatus of claim 1 , wherein a connector of the plurality of connectors comprises a first vertical conductor extending between an upper metal interconnect layer and a lower metal interconnect layer for the non-volatile memory, and a second vertical conductor extending between the upper metal interconnect layer and a word line layer exposed at one of the word line contact regions.

6. The apparatus of claim 5 , wherein a distance between adjacent first vertical conductors is smaller between word line contact regions than within word line contact regions.

7. The apparatus of claim 1 , wherein the word line contact region for the first tier and the word line contact region for the second tier are disposed at a first side of the array.

8. The apparatus of claim 7 , wherein a second word line contact region for the first tier and a second word line contact region for the second tier are disposed at a second side of the array.

9. The apparatus of claim 1 , wherein the plurality of word line contact regions comprises three or more word line contact regions separated by level regions.

10. The apparatus of claim 1 , wherein a step pitch for the word line contact regions is based on a block pitch for the word line switch transistors.

11. The apparatus of claim 1 , wherein a step pitch for the word line contact regions is independent of a block pitch for the word line switch transistors.

12. The apparatus of claim 1 , further comprising a decoder that generates the word line bias voltages, and a global bus for transmitting the word line voltages, wherein connections between the decoder and the global bus are routed within one or more metal layers above the three-dimensional non-volatile memory array.

13. The apparatus of claim 12 , wherein the connections are routed to a first edge of the array, then to the global bus at a second edge of the array.

14. A system comprising:
a non-volatile memory device comprising one or more non-volatile memory elements, wherein a non-volatile memory element comprises:
a three-dimensional non-volatile memory array comprising a stack of word line layers, the word line layers comprising word lines;
a plurality of word line switch transistors for transferring word line bias voltages to the word lines;
a plurality of word line contact regions comprising stepped structures for coupling the word line switch transistors to the word lines, wherein a first stepped structure for a first tier of word line layers is disposed apart from a second stepped structure for a second tier of word line layers; and
a plurality of connectors coupling the word line switch transistors to the word lines, the connectors comprising vertical conductors, wherein connectors for a single word line contact region comprise vertical conductors disposed within the single word line contact region, at a first side of the single word line contact region, and at a second side of the single word line contact region.

15. The system of claim 14 , wherein a region comprising the word line switch transistors is disposed under the word line contact regions.

16. The system of claim 14 , wherein a connector of the plurality of connectors comprises a first vertical conductor extending between an upper metal interconnect layer and a lower metal interconnect layer for the non-volatile memory, and a second vertical conductor extending between the upper metal interconnect layer and a word line layer exposed at one of the word line contact regions.

Assignees

• Sandisk Technologies Llc

Inventors

• Nguyen Qui
• Chu Alexander
• Louie Kenneth
• Amarnath Anirudh
• Yu Jixin
• Li Yen-Lung Jason
• Tseng Tai-Yuan
• Yuh Jong

Classifications

• G11C8/10

  Decoders · CPC title

• H01L27/112

  Electricity · mapped topic

• G11C8/08 Primary

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G06F13/4072

  Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002) · CPC title