Semiconductor device having active fin pattern at cell boundary

Patent metadata

Field	Value
Publication number	US-12034008-B2
Application number	US-202318336754-A
Country	US
Kind code	B2
Filing date	Jun 16, 2023
Priority date	Aug 21, 2020
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first standard cell and a second standard cell, the first standard cell and the second standard cell being disposed on a substrate, each of the first and second standard cells comprising an active region, a plurality of fin patterns disposed on the active region and extending in a first direction, a plurality of gate structures intersecting the plurality of fin patterns and extending in a second direction perpendicular to the first direction, a plurality of source/drain regions disposed on the plurality of fin patterns on both sides of each of the plurality of gate structures, and a contact structure connected to at least one of the plurality of source/drain regions and extending in a vertical direction, wherein the first and second standard cell are arranged in the second direction and shares a boundary with each other;
a power line disposed on a lower surface of the substrate and overlapping the boundary between the first standard cell and the second standard cell, the power line extending in the first direction;
a through conductive structure extending from the lower surface of the substrate toward an upper surface of the substrate, and connected to the power line; and
a buried conductive structure disposed on the substrate, and connected to the through conductive structure,
wherein the plurality of fin patterns of the first standard cell comprises an external fin pattern overlapping the power line in the vertical direction,
wherein the buried conductive structure is electrically connected to the contact structure and supplies power to the first standard cell and the second standard cell.

2. The semiconductor device of claim 1 , further comprising a device isolation layer disposed on the substrate, and defining the active region and the plurality of fin patterns.

3. The semiconductor device of claim 2 , wherein the buried conductive structure is buried in the device isolation layer.

4. The semiconductor device of claim 3 , wherein the buried conductive structure is located between the active region of the first standard cell and the active region of the second standard cell.

5. The semiconductor device of claim 1 , wherein the buried conductive structure extends in the second direction.

6. The semiconductor device of claim 1 , wherein the buried conductive structure has a portion extending into the substrate, and connected to the through conductive structure in the substrate.

7. The semiconductor device of claim 1 , wherein the contact structure comprises an extension portion extending in the second direction, and connected to the buried conductive structure.

8. The semiconductor device of claim 1 , wherein the plurality of gate structures comprises at least one gate structure extending from the first standard cell to pass through the boundary between the first standard cell and the second standard cell.

9. The semiconductor device of claim 1 , wherein the through conductive structure includes a conductive via extending from the lower surface of the substrate toward the upper surface of the substrate, and an insulating liner disposed between the conductive via and the substrate.

10. A semiconductor device comprising:
a plurality of standard cells arranged in a second direction on a substrate, each of the plurality of standard cells comprising two active regions, a plurality of fin patterns disposed on each of the two active regions and extending in a first direction perpendicular to the second direction, a plurality of gate structures intersecting the plurality of fin patterns and extending in the second direction, a plurality of source/drain regions disposed on the plurality of fin patterns on both sides of each of the plurality of gate structures, a contact structure connected to at least one of the plurality of source/drain regions;
a device isolation layer disposed on the substrate, and defining the two active regions and the plurality of fin patterns in each of the plurality of standard cells;
power lines disposed on a lower surface of the substrate, and extending in the first direction, the power lines arranged in a first pitch corresponding to a cell height of each of the plurality of standard cells;
through conductive structures respectively connected to the power lines, and extending toward an upper surface of the substrate between adjacent active regions of adjacent standard cells of the plurality of standard cells, the through conductive structures arranged in a second pitch different from the first pitch; and
buried conductive structures buried in the device isolation layer, and respectively connected to the through conductive structure, each of the buried conductive structures electrically connected to the contact structure.

11. The semiconductor device of claim 10 , wherein the through conductive structures comprises a first through conductive structure disposed on a first power line among the power lines, and
the first through conductive structure is shifted in the first direction from a center of the first power line.

12. The semiconductor device of claim 11 , wherein the through conductive structures comprises a second through conductive structure disposed on a second power line among the power lines, and
wherein the second through conductive structure is shifted from a center of the second power line in a direction opposite to the first direction or is located at the center of the second power line.

13. The semiconductor device of claim 10 , wherein the plurality of standard cells include first and second standard cells having different cell heights.

14. The semiconductor device of claim 10 , wherein the plurality of standard cells include first and second standard cells having adjacent to each other.

15. The semiconductor device of claim 14 , wherein the plurality of fin patterns of the first standard cell include an external fin pattern adjacent to the second standard cell, and the external fin pattern overlaps a corresponding power line among the power lines in a vertical direction.

16. The semiconductor device of claim 14 , wherein the plurality of gate structures comprises at least one gate structure extending from the first standard cell onto the second standard cell.

17. The semiconductor device of claim 10 , wherein the buried conductive structure extends in the second direction.

18. The semiconductor device of claim 10 , wherein the contact structure comprises an extension portion extending in the second direction, and connected to each of the buried conductive structures.

19. The semiconductor device of claim 10 , wherein each of the through conductive structure include a conductive via extending from the lower surface of the substrate toward the upper surface of the substrate, and an insulating liner disposed between the conductive via and the substrate.

20. A semiconductor device comprising:
a first standard cell and a second standard cell, the first standard cell and the second standard cell disposed on a substrate and having different cell heights, each of the first and second standard cells comprising two active regions, a plurality of fin patterns disposed on each of the two active regions and extending in a first direction, a plurality of gate structures intersecting the plurality of fin patterns and extending in a second direction perpendicular to the first direction, a plurality of source/drain regions disposed on the plurality of fin patterns on both sides of each of the plurality of gate structures, and a contact s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sanghoon
• Do Jungho
• Seo Jaewoo
• YU Jisu

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10D84/853

  comprising FinFETs · CPC title