Area efficient power switch

Patent metadata

Field	Value
Publication number	US-9817937-B2
Application number	US-201514880420-A
Country	US
Kind code	B2
Filing date	Oct 12, 2015
Priority date	Sep 27, 2012
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell.

First claim

What is claimed is:

1. A computer implemented method comprising:
receiving, in a cell library design tool, executed using a computer processor, a specification of a power switch circuit to be established as a power switch cell in a cell library;
receiving, in the cell library design tool, one or more attributes of the power switch cell including a height of the cell boundary, the height of the cell boundry being at least double a standard cell's height, wherein the standard cell's height is equivalent to the height of a doped well;
receiving, in the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells, the parallel rows of doped wells interleaved with a doped substrate, wherein the doping of the doped wells is of a different type than the doping of the substrate; and
generating, in the cell library design tool, one or more data files representing the power switch cell based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint.

2. The method of claim 1 , wherein:
the power switch cell further comprises a header cell configured for power-gating;
the parallel rows of doped wells comprise parallel rows of n-wells; and
the doped substrate further comprises a p-type substrate.

3. The method of claim 1 , wherein:
the power switch cell further comprises a footer cell configured for power-gating;
the parallel rows of doped wells comprise parallel rows of p-wells; and
the doped substrate further comprises an n-type substrate.

4. The method of claim 1 , further comprising:
receiving, in the cell library design tool, a layout placement constraint requiring the standard cell to be placed in the semiconductor layout in a column with the power switch cell, with a first portion of the standard cell facing the power switch cell and placed so as to be positioned on one of the rows of doped wells bridged by the power switch cell and with a second portion of the standard cell placed so as to be positioned on the doped substrate, wherein the first portion comprises logic of a type complementary to the doping of the wells, and the second portion comprises logic of a type complementary to the doping of the substrate.

5. The method of claim 4 , wherein the layout placement constraint requiring the standard cell to be placed in the semiconductor layout requires the power switch cell to have a height greater than the standard cell's height.

6. The method of claim 4 , wherein the layout placement constraint requiring the standard cell to be placed in the semiconductor layout requires the power switch cell to have a height at least double the standard cell's height.

7. The method of claim 1 , further comprising providing the one or more data files representing the power switch cell to a place-and-route tool, and generating, using the place-and-route tool, an integrated circuit layout that includes the power switch cell.

8. The method of claim 1 , wherein the one or more attributes of the power switch cell received in the cell library design tool are provided as input to the cell library design tool by a user of the cell library design tool.

9. A non-transitory computer readable storage medium including program instructions executable by a processor to:
receive a specification of a power switch circuit to be established as a power switch cell in a cell library;
receive one or more attributes of the power switch cell including a height of the cell boundary;
receive a first layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells, the parallel rows of doped wells interleaved with a doped substrate, wherein the doping of the doped wells is of a different type than the doping of the substrate;
receive a second layout placement constraint requiring a standard cell to be placed in the semiconductor layout in a column with the power switch cell, with a first portion of the standard cell facing the power switch cell and placed so as to be positioned on one of the rows of doped wells bridged by the power switch cell and with a second portion of the standard cell placed so as to be position on the doped substrate, wherein the first portion comprises logic of a type complementary to the doping of the wells, and the second portion comprises logic of a type complementry to the doping of the substrate; and
generate one or more data files representing the power switch cell based on the specification of the power switch circuit, the one or more attributes, the first layout placement constraint, and the second layout placement constraint.

10. The non-transitory computer readable storage medium of claim 9 , wherein the program instructions executable by the processor to receive one or more attributes of the power switch cell including the height of the cell boundary further comprise program instructions executable by the processor to receive the height of the cell boundary of greater than the standard cell's height, wherein the standard cell's height is equivalent to the height of a doped well.

11. The non-transitory computer readable storage medium of claim 9 , wherein the program instructions executable by the processor to receive one or more attributes of the power switch cell including the height of the cell boundary further comprise program instructions executable by the processor to receive the height of the cell boundary of at least double the standard cell's height, wherein the standard cell's height is equivalent to the height of a doped well.

12. The non-transitory computer readable storage medium of claim 9 , wherein:
the power switch cell further comprises a header cell configured for power-gating;
the parallel rows of doped wells comprise parallel rows of n-wells; and
the doped substrate comprises a p-type substrate.

13. The non-transitory computer readable storage medium of claim 9 , wherein:
the power switch cell further comprises a footer cell configured for power-gating;
the parallel rows of doped wells comprise parallel rows of p-wells; and
the doped substrate comprises an n-type substrate.

14. The non-transitory computer readable storage medium of claim 9 , wherein the standard cell has a height equivalent to the height of one of the doped wells, and the power switch cell has a height greater than the standard cell's height.

15. The non-transitory computer readable storage medium of claim 9 , wherein the standard cell has a height equivalent to the height of one of the doped wells, and the power switch cell has a height at least double the standard cell's height.

16. The non-transitory computer readable storage medium of claim 9 , wherein the first layout placement constraint is provided as input by a user of the processor.

17. A system comprising:
a non-transitory computer memory configured to store computer program instructions; and
a computer processor configured to execute the computer program instructions and to cause the system to:
receive, in a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library;
receive, in the cell library design tool, one or more attributes of the power switch cell including a height of the cell boundary comprising at least double a standard cell's height, wherein the standard cell's height is equivalent to the height of a doped well;
receive, in the cell library design tool, a layout placement constraint

Assignees

• Apple Inc

Inventors

• Suzuki Shingo
• Rajagopal Karthik
• Tang Bo

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F17/5072 Primary

  Physics · mapped topic