Integrated circuit devices

Patent metadata

Field	Value
Publication number	US-10249605-B2
Application number	US-201715655125-A
Country	US
Kind code	B2
Filing date	Jul 20, 2017
Priority date	Dec 7, 2016
Publication date	Apr 2, 2019
Grant date	Apr 2, 2019

Abstract

An integrated circuit (IC) device includes at least one standard cell. The at least one standard cell includes: first and second active regions respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction; first and second gate lines extending parallel to each other in a second direction perpendicular to the first direction across the first and second active regions, a first detour interconnection structure configured to electrically connect the first gate line with the second gate line; and a second detour interconnection structure configured to electrically connect the second gate line with the first gate line. The first and second detour interconnection structures include a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via.

First claim

What is claimed is:

1. An integrated circuit device comprising at least one standard cell, wherein the at least one standard cell comprises:
a first active region and a second active region respectively disposed on each of two sides of a dummy region, the first and second active regions having different conductivity types and extending in a first direction;
a first gate line and a second gate line extending parallel to each other in a second direction perpendicular to the first direction across the first active region and the second active region, wherein the first gate line comprises a first portion of the first gate line and a second portion of the first gate line, and the second gate line comprises a first portion of the second gate line and a second portion of the second gate line;
a first detour interconnection structure configured to electrically connect the first portion of the first gate line on the first active region with the second portion of the second gate line on the second active region; and
a second detour interconnection structure configured to electrically connect the first portion of the second gate line on the first active region with the second portion of the first gate line on the second active region,
wherein the first and second detour interconnection structures comprise a lower interconnection layer extending in the first direction, an upper interconnection layer extending in the second direction, and a contact via on at least one of the first active region and the second active region to connect the lower interconnection layer with the upper interconnection layer.

2. The integrated circuit device of claim 1 , wherein the first detour interconnection structure overlaps the first active region, the second active region, and the dummy region, and
wherein the second detour interconnection structure overlaps the first active region, the second active region, and the dummy region and is spaced apart from the first detour interconnection structure.

3. The integrated circuit device of claim 1 , further comprising:
a first gate contact disposed on the first portion of the first gate line on the first active region;
a second gate contact disposed on the second portion of the first gate line on the second active region;
a third gate contact disposed on the first portion of the second gate line on the first active region; and
a fourth gate contact disposed on the second portion of the second gate line on the second active region,
wherein the first and third gate contacts are in a staggered form relative to each other, or the second and fourth gate contacts are in a staggered form relative to each other.

4. The integrated circuit device of claim 3 , wherein the first gate contact, the second gate contact, the third gate contact, and the fourth gate contact have a width that is less than or equal to a pitch of the first gate line and the second gate line.

5. The integrated circuit device of claim 1 , further comprising a gate cutting layer on the dummy region across the first gate line and the second gate line, the gate cutting layer configured to separate the first gate line into the first portion of the first gate line and the second portion of the first gate line, and separate the second gate line into the first portion of the second gate line and the second portion of the second gate line.

6. The integrated circuit device of claim 5 , wherein a width of the gate cutting layer in the first direction is less than or equal to twice a pitch of the first gate line and the second gate line.

7. The integrated circuit device of claim 5 , wherein the lower interconnection layer comprises first through fourth lower interconnection layers, and
wherein one of the first and second lower interconnection layers is connected to the first portion of the first gate line, and another one of the first and second lower interconnection layers is connected to the first portion of the second gate line.

8. The integrated circuit device of claim 7 , wherein one of the third and fourth lower interconnection layers is connected to the second portion of the first gate line, and another one of the third and fourth lower interconnection layers is connected to the second portion of the second gate line.

9. The integrated circuit device of claim 7 , wherein the first and second lower interconnection layers are on the first active region, and
wherein the third and fourth lower interconnection layers are on the second active region.

10. The integrated circuit device of claim 7 , wherein at least a portion of any one of the second and third lower interconnection layers overlaps the dummy region.

11. The integrated circuit device of claim 1 , further comprising a common contact pad extending from a portion of the first active region between the first gate line and the second gate line to a portion of the second active region between the first gate line and the second gate line.

12. The integrated circuit device of claim 11 , further comprising an output via on the common contact pad located on the dummy region,
wherein the lower interconnection layer further comprises a fifth lower interconnection layer connected to the output via, and
wherein the fifth lower interconnection layer extends on the dummy region in the first direction.

13. An integrated circuit device comprising:
a first active region and a second active region respectively disposed on each of two sides of a dummy region, the first active region and the second active region having different conductivity types and extending in a first direction;
a first portion of a first gate line and a first portion of a second gate line extending parallel to each other on the first active region in a second direction perpendicular to the first direction;
a second portion of the first gate line and a second portion of the second gate line extending on the second active region in the second direction and arranged parallel to each other, the second portion of the first gate line and the second portion of the second gate line being disposed apart from the first portion of the first gate line and the first portion of the second gate line, respectively;
a first detour interconnection structure configured to electrically connect the first portion of the first gate line with the second portion of the second gate line; and
a second detour interconnection structure configured to electrically connect the first portion of the second gate line with the second portion of the first gate line,
wherein the first and second detour interconnection structures comprise a lower interconnection layer having a unidirectional structure extending in the first direction, an upper interconnection layer having a unidirectional structure extending in the second direction, and a contact via on at least one of the first active region and the second active region to connect the lower interconnection layer with the upper interconnection layer.

14. The integrated circuit device of claim 13 , further comprising:
a first gate contact disposed on the first portion of the first gate line;
a second gate contact disposed on the second portion of the first gate line;
a third gate contact disposed on the first portion of the second gate line; and
a fourth gate contact disposed on the second portion of the second gate line,
wherein the first and third gate contacts are in a staggered form relative to each other, or the second and fourth gate contacts are in a staggered form relative to each other.

15. The integrated circuit device of claim 14 , wherein one of the first and third gate contacts is connecte

Assignees

• Samsung Electronics Co Ltd

Inventors

• Subhash Kuchanuri
• Sidharth Rastogi
• Sharma Deepak
• Park Chul-Hong
• Yang Jae-Seok

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H01L23/5283

  Electricity · mapped topic

• H01L27/0207 Primary

  Electricity · mapped topic

• H01L27/1116

  Electricity · mapped topic

• H01L27/11807

  Electricity · mapped topic