Alignment mark structure and method for making

Patent metadata

Field	Value
Publication number	US-12033951-B2
Application number	US-202117404264-A
Country	US
Kind code	B2
Filing date	Aug 17, 2021
Priority date	May 7, 2021
Publication date	Jul 9, 2024
Grant date	Jul 9, 2024

Abstract

The reflectance of a low-reflectance alignment mark is increased by coating the alignment mark with a high-reflectance film layer. This improves the strength of the light signal and reduces variation in the light signal.

First claim

What is claimed is:

1. A method for increasing reflectance of an alignment mark in a photolithographic process, comprising:
defining the alignment mark in a photoresist layer which is over a low-reflectance substrate;
etching the alignment mark into the low-reflectance substrate;
removing the photoresist layer; and
depositing a high-reflectance film on the low-reflectance substrate that contains the alignment mark, the high-reflectance film having a higher reflectance than the low-reflectance substrate;
wherein the alignment mark comprises a plurality of trenches, wherein a trench top area is a sum of areas between the trenches and a trench bottom area is a sum of bottom areas of the trenches, and the ratio of the trench top area to the trench bottom area after deposition of the high-reflectance film is from about 0.8 to about 30.

2. The method of claim 1 , wherein a shield is used to prevent deposition of the high-reflectance film on a portion of the low-reflectance substrate that does not contain the alignment mark.

3. The method of claim 1 , wherein the high-reflectance film is deposited via sputtering.

4. The method of claim 1 , wherein the high-reflectance film comprises TiN, Cu, or Al.

5. The method of claim 1 , wherein the low-reflectance substrate comprises GaN or an Al/Ga/N/In alloy.

6. The method of claim 1 , further comprising:
depositing a photoresist on the portion of the high-reflectance film on the alignment mark;
removing the portion of the high-reflectance film not protected by the photoresist; and
removing the photoresist from the alignment mark.

7. The method of claim 6 , wherein the portion of the high-reflectance film not protected by the photoresist is removed using H 2 O 2 .

8. The method of claim 7 , further comprising removing GaO x generated by the reaction of GaN and H 2 O 2 .

9. The method of claim 8 , wherein the GaO x is removed using NH 4 OH.

10. The method of claim 1 , wherein the high-reflectance film has a thickness of from about 200 angstroms to about 1000 angstroms.

11. The method of claim 1 , wherein the reflectance is measured using a laser with a wavelength of about 632.8 nm.

12. A method for increasing reflectance of an alignment mark during production of an integrated circuit, comprising:
depositing a high-reflectance material to form a layer on a GaN film that contains the alignment mark, the high-reflectance material having a higher reflectance than the GaN film;
depositing photoresist on a portion of the high-reflectance layer on the alignment mark and leaving exposed a remaining portion of the high-reflectance layer;
removing the exposed portion of the high-reflectance layer from the GaN film;
removing the photoresist to expose the portion of the high-reflectance layer on the alignment mark; and
removing any non-GaN material from the GaN film.

13. The method of claim 12 , wherein the high-reflectance material is TiN.

14. The method of claim 12 , wherein the high-reflectance material is removed using an oxidizer.

15. The method of claim 12 , wherein the non-GaN material is GaOx.

16. The method of claim 12 , wherein the non-GaN material is removed using a base.

17. The method of claim 12 , wherein the high-reflectance layer has a thickness of from about 200 angstroms to about 800 angstroms.

18. An alignment mark on a low-reflectance substrate located upon a semiconducting wafer substrate, comprising a plurality of trenches in the low-reflectance substrate and a high-reflectance film deposited upon the plurality of trenches;
wherein the high-reflectance film has a higher reflectance than the low-reflectance substrate; and
wherein a trench top area is a sum of areas between the trenches and a trench bottom area is a sum of bottom areas of the trenches, and the ratio of the trench top area to the trench bottom area after deposition of the high-reflectance film is from about 0.8 to about 30.

19. The alignment mark of claim 18 , wherein the substrate is GaN and the high-reflectance film is TiN.

20. The alignment mark of claim 18 , wherein the plurality of trenches are parallel trenches; or
wherein the plurality of trenches includes horizontal trenches and vertical trenches; or
wherein the plurality of trenches are arranged to form a rectangular perimeter.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yeh Tzu-Hao
• Chen Kuan-Jung
• Lee Tsung-Lin
• Lin Shiuan-Jeng
• Chen Hung-Lin

Classifications

• H10W46/503

  Located in scribe lines · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• G03F9/7076

  Mark details, e.g. phase grating mark, temporary mark · CPC title

• G03F9/708 Primary

  Mark formation · CPC title