Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-11322682-B2
Application number	US-202117152703-A
Country	US
Kind code	B2
Filing date	Jan 19, 2021
Priority date	Jul 11, 2019
Publication date	May 3, 2022
Grant date	May 3, 2022

Abstract

A semiconductor structure is provided in the present invention, including a substrate having a device region and an alignment mark region defined thereon, a dielectric layer disposed on the substrate, a conductive via formed in the dielectric layer on the device region, a first trench formed in the dielectric layer on the alignment mark, a plurality of second trenches formed in the dielectric layer directly under the first trench and exposed from a bottom surface of the first trench, and a memory stacked structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the second trench.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate having a device region and an alignment mark region;
a dielectric layer disposed on the substrate;
a conductive via formed in the dielectric layer on the device region;
a first trench formed in the dielectric layer on the alignment mark region;
a plurality of second trenches formed in the dielectric layer under the first trench and exposed from a bottom surface of the first trench; and
a memory stack structure disposed on the dielectric layer, directly covering a top surface of the conductive via and filling into the first trench and the plurality of second trenches.

2. The semiconductor structure according to claim 1 , wherein the memory stack structure comprises a magnetoresistive random access memory (MRAM) structure, and the MRAM comprises:
a bottom electrode layer;
a magnetic tunneling junction (MTJ) layer;
a cap layer; and
a top electrode layer.

3. The semiconductor structure according to claim 1 , wherein the second trenches form an alignment mark feature, wherein the memory stack structure is patterned by a patterning process aligned to the alignment mark feature.

4. The semiconductor structure according to claim 1 , wherein the dielectric layer is not penetrated by the first trench and the second trenches.

5. The semiconductor structure according to claim 1 , wherein the bottom surface of the first trench is lower than a bottom surface of the conductive via.

6. The semiconductor structure according to claim 1 , wherein the second trenches have a same dimension.

7. The semiconductor structure according to claim 1 , wherein some of the second trenches extend along a first direction and arranged in parallel along a second direction, the other second trenches extend along the first direction and arranged in parallel along the second direction, wherein the first direction and the second direction are different.

8. The semiconductor structure according to claim 1 , wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer disposed on the first dielectric layer, wherein the first trench penetrates through the whole thickness of the second dielectric layer and an upper portion of the thickness of the first dielectric layer, the second trenches are formed completely in the first dielectric layer directly under the first trench.

9. The semiconductor structure according to claim 8 , further comprising an interconnecting structure formed in the first dielectric layer on the device region, wherein the conductive via is in the second dielectric layer vertically over the interconnecting structure and directly contacts the interconnecting structure.

10. The semiconductor structure according to claim 8 , wherein the first dielectric layer and the second dielectric layer comprise different dielectric materials.

Assignees

• United Microelectronics Corp

Inventors

• Wang hui-lin
• Hsu Chia-Chang
• Huang Rai-Min

Classifications

• H10W46/301

  for alignment · CPC title

• H10W46/00 Primary

  Marks applied to devices, e.g. for alignment or identification · CPC title

• H01L23/544

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic