Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-9268636-B2
Application number	US-201313910591-A
Country	US
Kind code	B2
Filing date	Jun 5, 2013
Priority date	Feb 26, 2013
Publication date	Feb 23, 2016
Grant date	Feb 23, 2016

Abstract

A memory controller includes a controller input/output circuit configured to output a first command to read first data, and output a second command to read an error corrected portion of the first data. A memory device includes: an error detector, a data storage circuit and an error correction circuit. The error detector is configured to detect a number of error bits in data read from a memory cell in response to a first command. The data storage circuit is configured to store the read data if the detected number of error bits is greater than or equal to a first threshold value. The error correction circuit is configured to correct the stored data.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array including a memory cell;
an error correction circuit configured to correct errors in data read from the memory cell in response to a first command from a memory controller, and to store the corrected data in one or more data buffers; and
a data output circuit configured to output the corrected data stored in the one or more data buffers to the memory controller in response to a second command from the memory controller,
wherein the second command is input after a delay time required to correct the errors in the data read from the memory cell after the first command is input.

2. The memory device of claim 1 , further comprising:
an error detector configured to detect a number of error bits in the read data in response to the first command; wherein
the error correction circuit is configured to correct the errors in the read data based on the detected number of error bits.

3. The memory device of claim 2 , wherein the error correction circuit is further configured to use one of a first error correction algorithm and a second error correction algorithm based on the detected number of error bits.

4. The memory device of claim 2 , wherein the error detector is configured to compare the detected number of error bits with at least one threshold value, and wherein the error correction circuit is configured to correct the errors in the read data based on the comparison.

5. The memory device of claim 4 , wherein the error correction circuit is configured to correct the errors in the data using a first error correction algorithm if the detected number of error bits is greater than or equal to a first threshold value, and wherein the error correction circuit is configured to correct the errors in the data using a second error correction algorithm if the detected number of error bits is greater than a second threshold value, but less than the first threshold value.

6. The memory device of claim 1 , further comprising:
an error correction status information generating circuit configured to output error correction status information based on the detected number of error bits.

7. The memory device of claim 6 , wherein the error correction status information indicates whether the detected number of error bits is greater than or equal to a first threshold value.

8. The memory device of claim 6 , wherein the error correction status information indicates whether the read data is correctable.

9. The memory device of claim 1 , wherein the second command is one of a read command and a buffer read command.

10. The memory device of claim 1 , further comprising:
a data storage circuit including the one or more data buffers, the data storage circuit being configured to store the read data to be corrected by the error correction circuit.

11. The memory device of claim 10 , wherein the data storage circuit is further configured to store a buffer status indicator in association with the read data.

12. The memory device of claim 10 , further comprising:
a management circuit configured to control output of the read data from the data storage circuit to the data output circuit based on the second command.

13. The memory device of claim 12 , wherein the data storage circuit includes a plurality of data buffers, and wherein the management circuit is configured to control output of the stored data from the plurality of data buffers to the data output circuit based on the second command and address information associated with the second command.

14. The memory device of claim 10 , further comprising:
an address matching circuit configured to output a matching signal based on a comparison between address information associated with the second command and address information associated with the data stored in the data storage circuit; and a management circuit configured to control output of the read data from the data storage circuit to the data output circuit based on the matching signal.

15. The memory device of claim 14 , wherein the data storage circuit includes a plurality of data buffers, and wherein the address matching circuit is configured to output the matching signal based on a comparison between address information associated with the second command and address information stored in association with the data stored in the plurality of data buffers.

16. The memory device of claim 15 , wherein the management circuit controls the data storage circuit to output the stored data to the data output circuit if the address information associated with the second command matches address information associated with the stored data.

17. A method of operating a memory device, the method comprising:
correcting errors in data read from a memory cell in response to a first command from a memory controller;
storing the corrected data in one or more data buffers; and
outputting the corrected data stored in the one or more data buffers to the memory controller in response to a second command from the memory controller,
wherein the second command is input after a delay time required to correct the errors in the data read from the memory cell after the first command is input.

18. The method of claim 17 , further comprising:
detecting a number of error bits in data read from the memory cell in response to the first command; and
storing the read data in the one or more data buffers if the detected number of error bits is greater than or equal to a first threshold value.

19. The method of claim 18 , further comprising:
checking a data storage status indicator in response to the second command, the data storage status indicator indicating whether the read data is stored in the one or more data buffers; and
wherein the outputting selectively outputs one of corrected data and second data from the memory cell based on the data storage status indicator.

20. The method of claim 17 , further comprising:
detecting a number of error bits in data read from the memory cell in response to the first command; and
outputting error correction status information associated with the read data, the error correction status information indicating whether the detected number of error bits is greater than or equal to a first threshold value.

Assignees

• Chung Hoi-Ju
• Kim Su-A
• Seo Mu-Jin
• Yu Hak-Soo
• Youn Jae-Youn
• Choi Hyo-Jin
• Samsung Electronics Co Ltd

Inventors

• Chung Hoi-Ju
• Kim Su-A
• Seo Mu-Jin
• Yu Hak-Soo
• Youn Jae-Youn
• Choi Hyo-Jin

Classifications

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1008

  in individual solid state devices (G06F11/1004 takes precedence) · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title