Apparatuses including capacitors and related systems

Patent metadata

Field	Value
Publication number	US-12010827-B2
Application number	US-202117304304-A
Country	US
Kind code	B2
Filing date	Jun 17, 2021
Priority date	May 28, 2020
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

An apparatus includes fin structures comprising individual levels of a conductive material having elongated portions extending in a first horizontal direction, first conductive lines extending in a second horizontal direction transverse to the first horizontal direction, and second conductive lines extending in a vertical direction transverse to each of the first horizontal direction and the second horizontal direction. At least portions of the first conductive lines are aligned vertically. The apparatus also includes horizontal capacitor structures comprising the conductive material of the fin structures and access devices proximate intersections of the first conductive lines and the second conductive lines. The access devices comprise the conductive material of the fin structures. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

First claim

What is claimed is:

1. An apparatus, comprising:
capacitors arranged in one or more columns above a base material;
first conductive lines extending substantially parallel to a major plane of the base material;
second conductive lines extending substantially transverse to the major plane of the base material, individual capacitors on respective levels sharing a common first conductive line, and individual columns of the capacitors sharing a common second conductive line, elongated portions of the individual capacitors extending substantially parallel to the major plane of the base material and substantially transverse to each of the first conductive lines and the second conductive lines, at least some of the elongated portions of the individual capacitors configured as electrodes of the capacitors; and
a common contact region located on a side of the first conductive lines opposite the capacitors, the common contact region connecting two or more of the elongated portions of the individual capacitors.

2. The apparatus of claim 1 , further comprising access devices comprising gate structures coupled to the second conductive lines, the individual capacitors and respective access devices sharing a common gate structure.

3. The apparatus of claim 2 , wherein the access devices comprise a conductive material common to the capacitors.

4. The apparatus of claim 2 , wherein the access devices are located in a first region and the capacitors are located in a second region laterally separated from the first region by a support structure extending in a direction substantially parallel to the first conductive lines.

5. An apparatus, comprising:
data lines extending in a first direction;
access lines extending in a second direction, orthogonal to the first direction;
capacitors adjacent to the access lines and comprising electrodes extending in a third direction, orthogonal to each of the first direction and the second direction, the capacitors comprising elongated structures including junctionless nanowires configured as the electrodes of the capacitors;
a staircase structure adjacent to one or more of a longitudinal end and a lateral side of the electrodes of the capacitors; and
conductive contacts on individual levels of the staircase structure, each of the capacitors corresponding to a respective level of the staircase structure sharing a common conductive contact.

6. The apparatus of claim 5 , further comprising gate structures adjacent to the staircase structure and aligned with one another in the second direction, one or more of the gate structures located on the electrodes of individual capacitors.

7. The apparatus of claim 5 , wherein portions of individual data lines are aligned with one another in the second direction, the data lines on a single level of the staircase structure sharing a common conductive contact.

8. The apparatus of claim 5 , wherein the capacitors corresponding to a single level of the staircase structure share a common data line.

9. The apparatus of claim 5 , wherein the staircase structure comprises contact pads on the individual levels thereof, individual contact pads on a single level sharing a common conductive material with a respective capacitor.

10. The apparatus of claim 5 , further comprising access devices proximate to intersections of the data lines and the access lines, individual access devices sharing a common conductive material with a respective data line.

11. A system, comprising:
a processor; and
electronic devices operably coupled to the processor, one or more of the electronic devices comprising:
capacitors overlying a material, a major plane of individual capacitors substantially parallel with a major plane of the material;
gate structures adjacent to the capacitors, one or more of the gate structures coupled to respective capacitors;
conductive lines connecting individual gate structures, the conductive lines extending substantially transverse to the major plane of the material, the individual gate structures laterally adjacent to respective capacitors;
access devices adjacent to the conductive lines, the individual capacitors and respective access devices sharing a common gate structure; and
nanowires extending substantially parallel with the major plane of the material, the individual capacitors and respective access devices sharing a common conductive material of the nanowires.

12. The system of claim 11 , wherein the capacitors individually comprise opposing conductive structures separated by an insulative material, a single gate structure coupled to each of the opposing conductive structures.

13. The system of claim 11 , wherein at least some of the access devices comprise gate-all-around access devices.

14. The system of claim 11 , wherein one or more of the electronic devices are configured as memory devices comprising a CMOS under array (CUA) region underlying the material, circuitry of the CUA region connected to the gate structures through conductive contacts extending through the material.

15. The system of claim 11 , wherein at least some of the nanowires are configured as bottom electrodes of the capacitors.

16. The system of claim 11 , wherein the common conductive material of the nanowires comprises a single dopant comprising a p-type dopant or an n-type dopant.

17. The system of claim 11 , further comprising dielectric support structures separating the individual capacitors from the respective access devices.

18. The system of claim 11 , further comprising:
additional conductive lines connecting individual nanowires with one another; and
a contact region adjacent to the additional conductive lines, at least a portion of the contact region exhibiting a stepped profile.

19. The system of claim 11 , wherein one or more of the electronic devices comprise:
an array of two or more device structures laterally adjacent one another with end regions of individual device structures proximal to one another;
staircase structures aligned along a single lateral side of the array; and
conductive contacts located on individual contact pads of the staircase structures.

20. The system of claim 19 , wherein an uppermost step of an individual staircase structure is adjacent to the access devices and additional steps descend with increased distance from the access devices.

Assignees

• Micron Technology Inc

Inventors

• Brewer William M
• Locke Christopher
• Campbell Kyle B

Classifications

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10D62/121 Primary

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title