Semiconductor devices including a recessed access device and methods of forming same

Patent metadata

Field	Value
Publication number	US-9449978-B2
Application number	US-201414148402-A
Country	US
Kind code	B2
Filing date	Jan 6, 2014
Priority date	Jan 6, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A semiconductor device comprises a recessed access device that includes a first pillar, a second pillar, a channel region connecting the first and second pillars, and a gate disposed over the channel region. The channel region has a width that is narrower than widths of the first pillar and the second pillar. An array of recessed access devices comprises a plurality of pillars protruding from a substrate, and a plurality of channel regions. Each channel region has a width that is less than about 10 nm and couples neighboring pillars to form a plurality of junctionless recessed access devices. A method of forming at least one recessed access device also comprises forming pillars over a substrate, forming at least a channel region coupled with the pillars, the channel region having a relatively narrow width, and forming a gate at least partially surrounding the channel region on at least three sides.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a recessed access device, including:
a first pillar protruding from a substrate;
a second pillar protruding from the substrate;
a channel region including a fin structure, the channel region extending in a first direction between the first pillar and the second pillar and connecting the first pillar and the second pillar, wherein the channel region has a width in a second direction that is orthogonal to the first direction that is narrower than a width of the first pillar and a width of the second pillar in the second direction; and
a gate disposed over the channel region, the gate including a saddle region at least partially surrounding the fin structure on three sides thereof, a lower portion of the channel region located above a lower portion of the gate.

2. The semiconductor device of claim 1 , wherein the first pillar, the second pillar, and the channel region are each formed from an N-type material and the substrate is formed from a P-type material.

3. The semiconductor device of claim 2 , wherein the first pillar and the second pillar are each formed from an N + semiconductor material, and the channel region is formed from an N − semiconductor material.

4. The semiconductor device of claim 1 , wherein the first pillar, the second pillar, and the channel region are each formed from a P-type material.

5. The semiconductor device of claim 4 , wherein the first pillar and the second pillar are each formed from a P + semiconductor material, and the channel region is formed from a P − semiconductor material.

6. The semiconductor device of claim 1 , wherein the width of the channel region is less than 10 nm.

7. The semiconductor device of claim 1 , wherein the first pillar and the second pillar have a higher doping concentration than a doping concentration of the channel region.

8. The semiconductor device of claim 1 , wherein each of the first pillar and the second pillar comprises a higher doping concentration at a top portion thereof than proximate the channel region.

9. The semiconductor device of claim 1 , wherein the first pillar comprises a source region, the second pillar comprises a drain region, and the channel region comprises an active region.

10. The semiconductor device of claim 1 , wherein the first pillar and the second pillar each comprise tapered sidewalls.

11. A semiconductor device, comprising:
at least a first pillar comprising a source region over a substrate;
at least a second pillar comprising a drain region laterally adjacent to the at least a first pillar;
a channel region extending from the at least a first pillar to the at least a second pillar in a first direction;
a gate between the at least a first pillar and the at least a second pillar;
a gate oxide between the gate and each of the at least a first pillar and the at least a second pillar; and
a word line connecting the gate to other gates between other pillars, the word line extending in a second direction that is orthogonal to the first direction.

12. The semiconductor device of claim 11 , wherein the at least a first pillar has a height that is greater than a height of the at least a second pillar.

13. The semiconductor device of claim 11 , wherein the at least a first pillar is coupled with a storage element of a memory cell and the at least a second pillar is coupled to a bit line of a memory array.

14. A semiconductor device, comprising:
a recessed access device, including:
a first pillar protruding from a substrate;
a second pillar protruding from the substrate;
a channel region extending in a first direction between the first pillar and the second pillar and connecting the first pillar and the second pillar, wherein the channel region has a width in a second direction that is orthogonal to the first direction that is narrower than a width of the first pillar and a width of the second pillar in the second direction; and
a gate disposed over the channel region;

a plurality of additional pillars protruding from the substrate; and
a plurality of channel regions, each channel region coupling neighboring pillars of the plurality of additional pillars to form an array of junctionless recessed access devices, wherein each channel region has a width that is less than about 10 nm.

15. The semiconductor device of claim 14 , wherein the array of junctionless recessed access device comprises the plurality of additional pillars and the plurality of channel regions all being N-type materials without a PN junction therebetween.

16. The semiconductor device of claim 14 , wherein the array of junctionless recessed access device comprises the plurality of additional pillars and the plurality of channel regions all being P-type materials without a PN junction therebetween.

17. The semiconductor device of claim 14 , wherein each channel region of the plurality of channel regions has a doping concentration that is relatively lower than a doping concentration of the pillars of the plurality of additional pillars.

18. The semiconductor device of claim 14 , further comprising a plurality of gates that extend along the array of junctionless recessed access devices over the plurality of channel regions.

19. The semiconductor device of claim 18 , wherein the plurality of gates includes a plurality of word lines of a memory array, each word line of the plurality of word lines extending in the orthogonal direction.

20. The semiconductor device of claim 14 , wherein at least one pillar of the plurality of additional pillars is shared by at least two neighboring junctionless recessed access devices of the array.

21. A method of forming at least one recessed access device, the method comprising:
forming at least a first pillar over a substrate;
forming at least a second pillar over the substrate;
forming at least a channel region including a fin structure and extending in a first direction between the at least a first pillar and the at least a second pillar coupled with the at least a first pillar and the at least a second pillar, the channel region having a width in a second direction that is orthogonal to the first direction that is narrower than a width of the at least a first pillar and a width of the at least a second pillar in the second direction; and
forming a gate within a recess between the first pillar and the second pillar, and including a saddle region at least partially surrounding the channel region on at least three sides, forming the gate within the recess comprising forming the gate such that a lower portion of the channel region is located above a lower portion of the gate.

22. The method of claim 21 , wherein forming at least a first pillar and forming at least a second pillar comprise:
forming a plurality of trenches in the first direction in a substrate;
forming a dielectric material within the trenches; and
forming another plurality of trenches in the substrate and the dielectric material in the second direction.

23. The method of claim 22 , wherein forming at least a channel region includes removing at least a portion of the pillars of at least another pillar to a desired width of the channel region, the at least another pillar located at an intersection of a first trench of the plurality of trenches and another trench of the another plurality of trenches.

Assignees

• Micron Technology Inc

Inventors

• Karda Kamal M
• Li Mingtao
• Liu Haitao
• Pandey Deepak Chandra
• Fischer Mark

Classifications

• H10D30/6218

  of the accumulation type · CPC title

• H10D64/025

  forming recessed gates, e.g. by using local oxidation · CPC title

• H10D30/0245 Primary

  by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H01L29/66613

  Electricity · mapped topic