Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator

Patent metadata

Field	Value
Publication number	US-9947687-B2
Application number	US-201615176624-A
Country	US
Kind code	B2
Filing date	Jun 8, 2016
Priority date	Jun 8, 2016
Publication date	Apr 17, 2018
Grant date	Apr 17, 2018

Abstract

A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V t 's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

First claim

The invention claimed is:

1. A memory cell, comprising:
a horizontally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V t 's of the programmable transistor, the programmable transistor comprising one source/drain region on one lateral side of the programmable transistor and another source/drain region on another lateral side of the programmable transistor that is opposite the one lateral side;
one select device electrically coupled in series with the one source/drain region of the programmable transistor, the one select device being on the one lateral side and elevationally outward of the programmable transistor;
another select device electrically coupled in series with the another source/drain region of the programmable transistor, the another select device being on the another lateral side and elevationally outward of the programmable transistor, the one select device and the another select device each comprising a diode;
one elevationally outer select line electrically coupled in series with and elevationally outward of the one select device; and
another elevationally outer select line electrically coupled in series with and elevationally outward of the another select device.

2. The memory cell of claim 1 wherein the one and another select devices are at the same elevation relative one another.

3. The memory cell of claim 1 wherein the one and another select lines are at the same elevation relative one another.

4. The memory cell of claim 1 wherein the gate insulator comprises programmable ferroelectric insulator material.

5. The memory cell of claim 1 wherein the gate insulator comprises programmable charge trapping insulator material.

6. The memory cell of claim 1 comprising an array of such memory cells.

7. A memory cell, comprising:
a horizontally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V t 's of the programmable transistor, the programmable transistor comprising one source/drain region on one lateral side of the programmable transistor and another source/drain region on another lateral side of the programmable transistor that is opposite the one lateral side;
one select device electrically coupled in series with the one source/drain region of the programmable transistor, the one select device being on the one lateral side and elevationally outward of the programmable transistor;
another select device electrically coupled in series with the another source/drain region of the programmable transistor, the another select device being on the another lateral side and elevationally outward of the programmable transistor;
one elevationally outer select line electrically coupled in series with and elevationally outward of the one select device;
another elevationally outer select line electrically coupled in series with and elevationally outward of the another select device; and
the programmable transistor having a channel region, and further comprising a conductive electrode directly against the channel region, the electrode extending to be directly against only one of the one or another source/drain region of the programmable transistor.

8. The memory cell of claim 7 wherein the one and another select device each comprise an elevationally extending transistor.

9. The memory cell of claim 8 wherein each of the elevationally extending transistors is vertical or within 10° of vertical.

10. The memory cell of claim 8 wherein the horizontally extending programmable field effect transistor is horizontal or within 10° of horizontal.

11. The memory cell of claim 1 wherein A memory cell, comprising:
a horizontally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V t 's of the programmable transistor, the programmable transistor comprising one source/drain region on one lateral side of the programmable transistor and another source/drain region on another lateral side of the programmable transistor that is opposite the one lateral side;
one select device electrically coupled in series with the one source/drain region of the programmable transistor, the one select device being on the one lateral side and elevationally outward of the programmable transistor;
another select device electrically coupled in series with the another source/drain region of the programmable transistor, the another select device being on the another lateral side and elevationally outward of the programmable transistor;
one elevationally outer select line electrically coupled in series with and elevationally outward of the one select device;
another elevationally outer select line electrically coupled in series with and elevationally outward of the another select device; and
the one select device and the another select device are two different type electrical components, one of the two different type electrical components being a field effect transistor, another of the two different type electrical components not being a field effect transistor.

12. A memory cell, comprising:
a horizontally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V t 's of the programmable transistor, the programmable transistor comprising one source/drain region on one lateral side of the programmable transistor and another source/drain region on another lateral side of the programmable transistor that is opposite the one lateral side;
one select device electrically coupled in series with the one source/drain region of the programmable transistor, the one select device being on the one lateral side and elevationally outward of the programmable transistor;
another select device electrically coupled in series with the another source/drain region of the programmable transistor, the another select device being on the another lateral side and elevationally outward of the programmable transistor;
one elevationally outer select line electrically coupled in series with and elevationally outward of the one select device;
another elevationally outer select line electrically coupled in series with and elevationally outward of the another select device; and
the one and another select device are each non-programmable field effect transistors having a respective conductive gate, a respective channel region, and a respective gate insulator there-between; the respective conductive gates and respective gate insulator completely encircling their respective channel regions.

13. A memory cell, comprising:
a horizontally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different V t 's of the horizontally extending programmable transistor, the horizontally extending programmable transistor comprising one source/drain region on one lateral side of the horizontally extending programmable transistor and another source/drain region on another lateral side of the horizontally extending programmable transistor that is opposite the one lateral side;
one elevationally extending field effect transistor comprising and sharing the one source source/drain region of the horizontally extending programmable transistor thereby directly electrically coupling the one elevationally extending field effect transistor and the horizontally extending progr

Assignees

• Micron Technology Inc

Inventors

• Bedeschi Ferdinando

Classifications

• H01L29/7827

  Electricity · mapped topic

• H01L27/11597 Primary

  Electricity · mapped topic

• H01L29/42392

  Electricity · mapped topic

• H01L27/1159

  Electricity · mapped topic

• H01L29/78391

  Electricity · mapped topic