Semiconductor package

Patent metadata

Field	Value
Publication number	US-12009277-B2
Application number	US-202217866866-A
Country	US
Kind code	B2
Filing date	Jul 18, 2022
Priority date	Jun 28, 2019
Publication date	Jun 11, 2024
Grant date	Jun 11, 2024

Abstract

A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first semiconductor chip and a second semiconductor chip on a substrate, the first and second semiconductor chips being equal in thickness such that uppermost faces of the first and second semiconductor chips are located at a same height from the substrate;
a barrier layer having an opening that exposes a first portion of the uppermost face of the first semiconductor chip, the barrier layer being in contact with a second portion of the uppermost face of the first semiconductor chip not exposed by the opening and an entirety of the uppermost face of the second semiconductor chip and; and
a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.

2. The semiconductor package as claimed in claim 1 , wherein a thickness of the heat transfer part is greater than a thickness of the barrier layer.

3. The semiconductor package as claimed in claim 1 , wherein the heat transfer part on the first semiconductor chip has substantially the same thickness as the heat transfer part on the barrier layer.

4. The semiconductor package as claimed in claim 1 , wherein the heat transfer part on the first semiconductor chip is thicker than the heat transfer part on the barrier layer.

5. The semiconductor package as claimed in claim 1 , wherein the barrier layer includes a photosensitive polymer.

6. The semiconductor package as claimed in claim 1 , wherein:
the heat transfer part includes an adhesive metal layer and a heat transfer material layer on an upper face of the adhesive metal layer, and
an undercut region is formed at an end of the adhesive metal layer.

7. The semiconductor package as claimed in claim 1 , wherein:
the heat transfer part includes an adhesive metal layer and a heat transfer material layer on an upper face of the adhesive metal layer, and
a portion of the heat transfer part is in contact with the first portion of the uppermost face of the first semiconductor chip.

8. The semiconductor package as claimed in claim 1 , wherein the first semiconductor chip is a logic chip, the second semiconductor chip is a memory chip, and the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the substrate.

9. The semiconductor package as claimed in claim 1 , further comprising a heat slug on the heat transfer part.

10. A semiconductor package, comprising:
a first semiconductor chip on a substrate, the first semiconductor chip having an uppermost face located at a first height from the substrate;
a second semiconductor chip on the substrate, the second semiconductor chip having an uppermost face located at the first height from the substrate such that the uppermost faces of the first and second semiconductor chips are located at a same level;
a heat transfer part on the first semiconductor chip and the second semiconductor chip, the heat transfer part being in contact with the uppermost face of the first semiconductor chip, and not contacting the second semiconductor chip; and
a heat slug in contact with at least a portion of the heat transfer part.

11. The semiconductor package as claimed in claim 10 , wherein a thickness of the heat transfer part on the first semiconductor chip is substantially the same as a thickness of the heat transfer part on the second semiconductor chip.

12. The semiconductor package as claimed in claim 11 , wherein the heat slug is in contact with the heat transfer part on the first semiconductor chip and not in contact with the heat transfer part on at least a portion of the second semiconductor chip.

13. The semiconductor package as claimed in claim 10 , wherein the heat transfer part on the first semiconductor chip is thicker than the heat transfer part on the second semiconductor chip.

14. The semiconductor package as claimed in claim 10 , further comprising a barrier layer between the second semiconductor chip and the heat transfer part.

15. The semiconductor package as claimed in claim 14 , wherein the heat transfer part is thicker than the barrier layer.

16. The semiconductor package as claimed in claim 10 , wherein an undercut region is formed at an end of the heat transfer part.

17. The semiconductor package as claimed in claim 10 , wherein the heat slug extends from one side of the substrate to the other side of the substrate.

18. A semiconductor package, comprising:
a substrate;
a first semiconductor chip on the substrate;
a second semiconductor chip on the substrate, an uppermost face of the second semiconductor chip being located at a same height as an uppermost face of the first semiconductor chip;
a molding part on the substrate, wrapping the first semiconductor chip and the second semiconductor chip, and exposing the uppermost face of the first semiconductor chip and the uppermost face of the second semiconductor chip, an uppermost face of the molding part being located at the same height as the uppermost face of the first semiconductor chip;
a barrier layer including an opening through which a first portion of the uppermost face of the first semiconductor chip is exposed, the barrier layer covering the second semiconductor chip and a second portion of the uppermost face of the first semiconductor chip not exposed by the opening; and
a heat transfer part on the barrier layer and in direct contact with the first portion of the uppermost face of the first semiconductor chip exposed by the opening.

19. The semiconductor package as claimed in claim 18 , further comprising a heat slug on the heat transfer part.

20. The semiconductor package as claimed in claim 18 , wherein:
the second semiconductor chip has a structure in which a plurality of memory chips is stacked, and
each memory chip is thinner than the first semiconductor chip.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong Kyu
• Park Jung-Ho
• Kim Jong Youn
• Jang Yeon Ho
• Jang Jae Gwon

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10P72/7418

  of passive members, e.g. a chip mounting substrate · CPC title