Semiconductor package

Patent metadata

Field	Value
Publication number	US-11404346-B2
Application number	US-202016743284-A
Country	US
Kind code	B2
Filing date	Jan 15, 2020
Priority date	Jun 28, 2019
Publication date	Aug 2, 2022
Grant date	Aug 2, 2022

Abstract

A semiconductor package includes a first semiconductor chip and a second semiconductor chip on a substrate, a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening through which at least a part of the first semiconductor chip is exposed, and a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a first semiconductor chip and a second semiconductor chip on a substrate, the first and second semiconductor chips being equal in thickness such that uppermost faces of the first and second semiconductor chips are located at a same height from the substrate;
a barrier layer on the first semiconductor chip and the second semiconductor chip, the barrier layer having an opening that exposes the uppermost face of the first semiconductor chip; and
a heat transfer part on the barrier layer, the heat transfer part extending along an upper face of the barrier layer and filling the opening, wherein:
the barrier layer extends continuously across an entirety of the uppermost face of the second semiconductor chip, and
the opening has a width, in a direction parallel to the uppermost face of the first semiconductor chip, that is the same as or less than a width of the uppermost face of the first semiconductor chip.

2. The semiconductor package as claimed in claim 1 , wherein a thickness of the heat transfer part is greater than a thickness of the barrier layer.

3. The semiconductor package as claimed in claim 1 , wherein the heat transfer part on the first semiconductor chip has substantially the same thickness as the heat transfer part on the barrier layer.

4. The semiconductor package as claimed in claim 1 , wherein the heat transfer part on the first semiconductor chip is thicker than the heat transfer part on the barrier layer.

5. The semiconductor package as claimed in claim 1 , wherein the barrier layer includes a photosensitive polymer.

6. The semiconductor package as claimed in claim 1 , wherein the heat transfer part includes an adhesive metal layer and a heat transfer material layer on an upper face of the adhesive metal layer, and an undercut region is formed at an end of the adhesive metal layer.

7. The semiconductor package as claimed in claim 1 , wherein the width of the opening is less than the width of the uppermost face of the first semiconductor chip, and the barrier layer is in contact with a part of the uppermost face of the first semiconductor chip.

8. The semiconductor package as claimed in claim 7 , wherein:
the heat transfer part includes an adhesive metal layer and a heat transfer material layer on an upper face of the adhesive metal layer,
the heat transfer material layer includes copper, and
a portion of the heat transfer part is in direct contact with the uppermost face of the first semiconductor chip, and no portion of the heat transfer part is in direct contact with the second semiconductor chip.

9. The semiconductor package as claimed in claim 1 , wherein the first semiconductor chip is a logic chip, the second semiconductor chip is a memory chip, and the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the substrate.

10. A semiconductor package, comprising:
a first semiconductor chip on a substrate, the first semiconductor chip having an uppermost face located at a first height from the substrate;
a second semiconductor chip on the substrate and spaced apart from the first semiconductor chip, the second semiconductor chip having an uppermost face located at the first height from the substrate such that the uppermost faces of the first and second semiconductor chips are located at a same level; and
a heat transfer part on the first semiconductor chip and the second semiconductor chip, the heat transfer part being in direct contact with the uppermost face of the first semiconductor chip, and not contacting the second semiconductor chip.

11. The semiconductor package as claimed in claim 10 , wherein a thickness of the heat transfer part on the first semiconductor chip is substantially the same as a thickness of the heat transfer part on the second semiconductor chip.

12. The semiconductor package as claimed in claim 10 , wherein the heat transfer part on the first semiconductor chip is thicker than the heat transfer part on the second semiconductor chip.

13. The semiconductor package as claimed in claim 10 , further comprising a barrier layer between the second semiconductor chip and the heat transfer part.

14. The semiconductor package as claimed in claim 13 , wherein the barrier layer includes a photosensitive polymer.

15. The semiconductor package as claimed in claim 13 , wherein the heat transfer part is thicker than the barrier layer.

16. The semiconductor package as claimed in claim 10 , wherein an undercut region is formed at an end of the heat transfer part.

17. The semiconductor package as claimed in claim 10 , wherein the first semiconductor chip and the second semiconductor chip are electrically connected to each other through the substrate.

18. A semiconductor package, comprising:
a substrate;
a molding part on the substrate and including a first trench and a second trench through which an upper face of the substrate is exposed;
a first semiconductor chip in the first trench and electrically connected to the substrate, an uppermost face of the first semiconductor chip being exposed by the molding part;
a second semiconductor chip in the second trench and electrically connected to the substrate, an uppermost face of the second semiconductor chip being exposed by the molding part and being located at a same height as the uppermost face of the first semiconductor chip;
a barrier layer on an upper face of the molding part, the barrier layer covering the second semiconductor chip and including an opening through which at least a part of the uppermost face of the first semiconductor chip is exposed; and
a heat transfer part on the barrier layer and in direct contact with the at least a part of the uppermost face of the first semiconductor chip exposed by the opening,
wherein the first trench and the second trench each extend continuously from the upper face of the substrate to the barrier layer.

19. The semiconductor package as claimed in claim 18 , further comprising a heat slug that surrounds an outer side face of the heat transfer part and an outer side face of the molding part.

20. The semiconductor package as claimed in claim 18 , wherein the barrier layer includes a photosensitive polymer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong Kyu
• Park Jung-Ho
• Kim Jong Youn
• Jang Yeon Ho
• Jang Jae Gwon

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10P72/7418

  of passive members, e.g. a chip mounting substrate · CPC title