Semiconductor packages including heat transferring blocks and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10170456-B2
Application number	US-201715635600-A
Country	US
Kind code	B2
Filing date	Jun 28, 2017
Priority date	Dec 19, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A semiconductor package may be provided. The semiconductor package may include a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer. The semiconductor package may include a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer. Related methods are also provided.

First claim

What is claimed is:

1. A semiconductor package comprising:
a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer and laterally spaced apart from each other;
a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer;
an encapsulant filling spaces between the heat transferring block and the first and second semiconductor chips and covering sidewalls of the first and second semiconductor chips; and
a heat dissipation layer connected to a top surface of the heat transferring block opposite to the interconnection layer and extending to cover a top surface of the encapsulant,
wherein the heat transferring block emits heat trapped in a region of the encapsulant between the first and second semiconductor chips,
wherein the heat transferring block comprises a through via to emit the heat, and
the through via is electrically isolated from the interconnection layer and the first and second semiconductor chips.

2. The semiconductor package of claim 1 ,
wherein the heat transferring block is configured to reduce the thermal stress applied to the semiconductor package by including a block body having a material including a thermal conductivity which is higher than a thermal conductivity of a material of the encapsulant.

3. The semiconductor package of claim 1 ,
wherein the heat transferring block includes a block body, and
wherein the heat transferring block is configured to reduce the thermal stress applied to the semiconductor package by reducing a total amount of the encapsulant with a volume of a block body.

4. The semiconductor package of claim 1 ,
wherein the heat transferring block includes a block body, and
wherein the heat transferring block is configured to reduce the thermal stress applied to the semiconductor package by including the block body having a coefficient of thermal expansion substantially equal to a coefficient of thermal expansion of the first and second semiconductor chips.

5. The semiconductor package of claim 1 ,
wherein the heat transferring block is configured to reduce the thermal stress applied to the semiconductor package by including a material configured to suppress defects generated in the semiconductor package by thermal stress which is due to a difference between thermal expansion coefficients of the block body and the first and second semiconductor chips.

6. The semiconductor package of claim 1 ,
wherein the heat transferring block includes a block body, and
wherein the heat transferring block is configured to reduce the thermal stress applied to the semiconductor package by including the block body having a semiconductor material.

7. The semiconductor package of claim 1 , wherein the heat transferring block includes:
a block body configured to have a top surface facing the heat dissipation layer and a bottom surface facing the interconnection layer; and
a plurality of through vias penetrating the block body,
wherein upper ends of the plurality of through vias are exposed at the top surface of the block body, and lower ends of the plurality of through vias are exposed at the bottom surface of the block body.

8. The semiconductor package of claim 7 , wherein the block body has a shape of a silicon die.

9. The semiconductor package of claim 7 , wherein the block body has a width which is greater than widths of the first and second semiconductor chips, in a direction that is substantially perpendicular to a direction along which the first and second semiconductor chips are arrayed.

10. The semiconductor package of claim 7 , wherein the plurality of through vias are comprised of a material having a thermal conductivity which is higher than a thermal conductivity of the block body.

11. The semiconductor package of claim 7 , wherein the plurality of through vias are comprised of a metal material.

12. The semiconductor package of claim 11 , wherein the plurality of through vias are comprised of a copper material.

13. The semiconductor package of claim 1 ,
wherein the interconnection layer includes first redistributed patterns, second redistributed patterns and third redistributed patterns;
wherein a first group of the third redistributed patterns are coupled to the first semiconductor chip, and a second group of the third redistributed patterns are coupled to the second semiconductor chip;
wherein at least one of the second redistributed patterns electrically connects one of the first group of the third redistributed patterns to one of the second group of the third redistributed patterns; and
wherein an end of the at least one of the second redistributed patterns overlaps with an end of the first semiconductor chip, and the other end of the at least one of the second redistributed patterns overlaps with an end of the second semiconductor chip.

14. The semiconductor package of claim 13 , wherein the first group of the third redistributed patterns are coupled to the first semiconductor chip through first inter connectors, and the second group of the third redistributed patterns are coupled to the second semiconductor chip through second inter connectors.

15. The semiconductor package of claim 1 ,
wherein the first semiconductor chip includes an application processor chip; and
wherein the second semiconductor chip includes a memory device receiving data from the first semiconductor chip or outputting data to the first semiconductor chip.

16. The semiconductor package of claim 1 ,
wherein the interconnection layer is configured to include paths used in data communication between the first and second semiconductor chips.

17. A semiconductor package comprising:
an interconnection layer and a heat sink pattern;
a first semiconductor chip and a second semiconductor chip disposed on the interconnection layer and laterally spaced apart from each other;
a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer and to be coupled to the heat sink pattern;
an encapsulant filling spaces between the heat transferring block and the first and second semiconductor chips and covering sidewalls of the first and second semiconductor chips; and
a heat dissipation layer connected to a top surface of the heat transferring block opposite to the interconnection layer and extending to cover a top surface of the encapsulant,
wherein the heat transferring block comprises a through via to emit the heat, and
the through via and the heat sink pattern are electrically isolated from the interconnection layer and the first and second semiconductor chips.

18. A semiconductor package comprising:
a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer and spaced apart from each other;
a heat transferring block disposed between the first and second semiconductor chips and bonded to the interconnection layer by an adhesive layer;
an encapsulant filling spaces between the heat transferring block and the first and second semiconductor chips and covering sidewalls of the first and second semiconductor chips; and
a heat dissipation layer connected to a top surface of the heat transferring block opposite to the interconnection layer and extending to cover a top surface of the encapsulant,
wherein the adhesive layer bonds the interconnection layer to a bottom surface of the heat transferring block,
wherein the heat transferring block emits heat trapped in a region of the encapsulant between the first and second semi

Assignees

• Sk Hynix Inc

Inventors

• Sung Ki Jun
• Jeong Rae Hyung

Classifications

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title