Three-dimensional semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-12004350-B2
Application number	US-202217819355-A
Country	US
Kind code	B2
Filing date	Aug 12, 2022
Priority date	Feb 7, 2018
Publication date	Jun 4, 2024
Grant date	Jun 4, 2024

Abstract

A three-dimensional (3D) semiconductor memory device includes a source conductive pattern on a substrate and extending in parallel to a top surface of the substrate, and an electrode structure including an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source conductive pattern in a first direction perpendicular to the top surface of the substrate.

First claim

What is claimed is:

1. A three-dimensional (3D) semiconductor memory device, comprising:
a source structure on a substrate and extending in parallel to a top surface of the substrate; and
an electrode structure comprising an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source structure in a first direction that is perpendicular to the top surface of the substrate,
wherein the erase control gate electrode is a lowest one of the gate structure and has a first thickness in the first direction, the ground selection gate electrode is a second lowest one of the gate structure and has a second thickness in the first direction, a lowermost one of the cell gate electrodes is a third lowest one of the gate structure, and each of the cell gate electrodes has a third thickness in the first direction,
wherein the first thickness is greater than both the second thickness and the third thickness,
wherein the ground selection gate electrode is spaced apart from the erase control gate electrode by a first maximum distance and is spaced apart from the lowermost one of the cell gate electrodes by a second maximum distance in the first direction, and
wherein the second maximum distance is greater than the first maximum distance.

2. The 3D semiconductor memory device of claim 1 , further comprising a vertical semiconductor pattern penetrating the electrode structure and the source structure,
wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure.

3. The 3D semiconductor memory device of claim 2 , wherein the vertical semiconductor pattern has a bottom surface located at a level lower than that of a bottom surface of the source structure.

4. The 3D semiconductor memory device of claim 1 , wherein the source structure comprises:
a first source conductive pattern on the substrate; and
a second source conductive pattern in contact with a top surface of the first source conductive pattern.

5. The 3D semiconductor memory device of claim 4 , wherein the first source conductive pattern comprises an additional portion having a recessed sidewall, and
wherein the second source conductive pattern is formed on, and covers, at least a portion of the top surface of the first source conductive pattern; and
wherein the second source conductive pattern is formed on, and covers, at least a portion of the recessed sidewall of the first source conductive pattern.

6. The 3D semiconductor memory device of claim 4 , wherein the first source conductive pattern and the second source conductive pattern each comprise a semiconductor material doped with dopants of a first conductivity type, and
wherein a first concentration of the dopants in the first source conductive pattern is greater than a second concentration of the dopants in the second source conductive pattern.

7. The 3D semiconductor memory device of claim 4 , wherein the first source conductive pattern comprises:
a horizontal portion extending in parallel to the electrode structure under the electrode structure; and
a sidewall portion extending from the horizontal portion in the first direction and surrounding a portion of a sidewall of a vertical semiconductor pattern penetrating the electrode structure and the source structure.

8. The 3D semiconductor memory device of claim 7 , further comprising:
a data storage pattern extending in the first direction between the vertical semiconductor pattern and the electrode structure,
wherein a bottom surface of the data storage pattern is in contact with the sidewall portion of the first source conductive pattern.

9. The 3D semiconductor memory device of claim 8 , wherein the data storage pattern has a fourth thickness on the sidewall of the vertical semiconductor pattern,
wherein the sidewall portion of the first source conductive pattern has a fifth thickness on the sidewall of the vertical semiconductor pattern, and wherein the fifth thickness of the sidewall portion of the first source conductive pattern is equal to the fourth of the data storage pattern.

10. The 3D semiconductor memory device of claim 8 , further comprising:
a dummy data storage pattern vertically spaced apart from the data storage pattern and the source structure.

11. A three-dimensional (3D) semiconductor memory device, comprising:
a source structure on a substrate and extending in parallel to a top surface of the substrate; and
an electrode structure comprising an erase control gate electrode, a ground selection gate electrode, cell gate electrodes, and a string selection gate electrode, which are sequentially stacked on the source structure in a first direction that is perpendicular to the top surface of the substrate,
wherein the erase control gate electrode is a lowest one of the electrode structure and has a first thickness in the first direction, the ground selection gate electrode is a second lowest one of the electrode structure and has a second thickness in the first direction, a lowermost one of the cell gate electrodes is a third lowest one of the electrode structure, and each of the cell gate electrodes has a third thickness in the first direction,
wherein the ground selection gate electrode is spaced apart from the erase control gate electrode by a first maximum distance in the first direction,
wherein the ground selection gate electrode is spaced apart from a first cell gate electrode of the cell gate electrodes by a second maximum distance in the first direction, the first cell gate electrode being the lowermost one of the cell gate electrodes in the first direction, and
wherein the second maximum distance is greater than the first maximum distance.

12. The 3D semiconductor memory device of claim 11 , wherein the first cell gate electrode is between the ground selection gate electrode and a second cell gate electrode of the cell gate electrodes.

13. The 3D semiconductor memory device of claim 11 , wherein the second maximum distance is greater than the third thickness.

14. The 3D semiconductor memory device of claim 11 , wherein the second maximum distance is greater than a third distance between two of the cell gate electrodes that are adjacent to each other in the first direction.

15. The 3D semiconductor memory device of claim 11 , further comprising a vertical semiconductor pattern penetrating the electrode structure and the source structure,
wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure.

16. The 3D semiconductor memory device of claim 11 , wherein the source structure comprises:
a first source conductive pattern on the substrate; and
a second source conductive pattern in contact with a top surface of the first source conductive pattern,
wherein the first source conductive pattern and the second source conductive pattern each comprise a semiconductor material doped with dopants of a first conductivity type, and
wherein a first concentration of the dopants in the first source conductive pattern is greater than a second concentration of the dopants in the second source conductive pattern.

17. The 3D semiconductor memory device of claim 16 , further comprising a vertical semiconductor pattern that extends in the first direction,
wherein the first source conductive pattern is in contact with a portion of a sidewall of the vertical semiconductor pattern.

18. The 3D semiconductor memory device of claim 17 , wherein the first source conductiv

Assignees

• Samsung Electronics Co Ltd

Inventors

• JUNG Euntaek
• Shin Joongshik
• Hong Sangjun

Classifications

• H10D30/696

  having at least one additional gate, e.g. program gate, erase gate or select gate · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title