Method of making a contact structure

Patent metadata

Field	Value
Publication number	US-11996361-B2
Application number	US-202217885026-A
Country	US
Kind code	B2
Filing date	Aug 10, 2022
Priority date	Feb 26, 2021
Publication date	May 28, 2024
Grant date	May 28, 2024

Abstract

A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.

First claim

What is claimed is:

1. A method of making a semiconductor device, the method comprising:
etching an insulating layer to form a first opening and a second opening;
depositing a conductive material in the first opening after forming the second opening;
performing a surface modification deposition process on the conductive material;
depositing, after the surface modification deposition process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer; and
depositing a conductive fill over the first liner layer, wherein the conductive fill comprises a different material from the conductive material.

2. The method of claim 1 , wherein depositing the first liner layer comprises depositing the first liner layer having a first thickness over the conductive material and a second thickness over the insulating layer, and the second thickness is greater than the first thickness.

3. The method of claim 1 , wherein depositing the conductive material comprises depositing ruthenium or tungsten.

4. The method of claim 1 , wherein performing the surface modification deposition comprises depositing a monolayer of an organic long chain molecule.

5. The method of claim 1 , further comprising depositing a second liner layer over the first liner layer, wherein the second liner layer is between the first liner layer and the conductive fill, and a thickness of the second liner layer is substantially uniform.

6. A method of making a semiconductor device, the method comprising:
etching an insulating layer to form a first opening and a second opening;
performing a surface modification deposition process on a conductive material exposed by the first opening;
depositing, after the surface modification deposition process, a first liner layer, wherein the first liner layer extends over the conductive material, and a thickness of the first liner layer over the conductive material is less than a thickness of the first liner layer over a top surface of the insulating layer; and
depositing a conductive fill over the first liner layer, wherein the conductive fill comprises a different material from the conductive material.

7. The method of claim 6 , further comprising depositing the conductive material in the first opening.

8. The method of claim 7 , wherein depositing the conductive material comprises filling less than an entirety of the first opening with the conductive material.

9. The method of claim 6 , wherein performing the surface modification deposition comprises depositing a monolayer of an organic long chain molecule.

10. The method of claim 6 , wherein performing the surface modification deposition comprises depositing a monolayer of benzotriazole (BTA).

11. The method of claim 6 , wherein performing the surface modification deposition comprises performing the surface modification on the conductive material having a top-most surface below a bottommost surface of the insulating layer.

12. The method of claim 6 , wherein depositing the first liner layer comprises depositing the first liner layer across an entirety of a top-most surface of the conductive layer exposed by the first opening.

13. The method of claim 6 , wherein depositing the first liner layer comprises depositing the first liner layer across less than an entirety of a top-most surface of the conductive layer exposed by the first opening.

14. The method of claim 6 , wherein further comprising depositing a second liner layer over the first liner layer.

15. The method of claim 6 , wherein depositing the conductive fill comprises depositing the conductive fill in both the first opening and the second opening.

16. The method of claim 6 , wherein depositing the conductive fill comprises depositing the conductive fill in the second opening.

17. A method of making a semiconductor device, the method comprising:
etching an insulating layer to form a first opening and a second opening;
performing a surface modification deposition process on a conductive material exposed by the first opening;
depositing, after the surface modification deposition process, a first liner layer, wherein the first liner layer extends from inside the first opening to the second opening; and
depositing a conductive fill over the first liner layer, wherein the conductive fill comprises a different material from the conductive material.

18. The method of claim 17 , wherein depositing the first liner layer comprises depositing the first liner layer along an entirety of a sidewall of the first opening and along an entirety of a sidewall of the second opening.

19. The method of claim 17 , wherein depositing the first linear layer comprises depositing the first liner layer along less than an entirety of a sidewall of the first opening.

20. The method of claim 17 , wherein performing the surface modification deposition process comprises depositing a monolayer of an organic long chain molecule.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chin Shu-Cheng
• Liu Yao-Min
• Su Hung-Wen
• Chi Chih-Chien
• Lin Chi-Feng

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10W20/438

  Interconnections with multiple fill metals, e.g. having different metals in wide and narrow interconnections, or having different metals in vias and in trenches · CPC title

• H10W20/4403

  based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence) · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/084 Primary

  for dual-damascene structures · CPC title