Plurality of stacked transistors attached by solder balls

Patent metadata

Field	Value
Publication number	US-11984387-B2
Application number	US-202217653397-A
Country	US
Kind code	B2
Filing date	Mar 3, 2022
Priority date	Sep 13, 2021
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A first chip includes a first surface, a second surface, a first semiconductor layer including a nitride semiconductor layer, a first electrode pad located at the first surface, a second electrode pad located at the first surface, a first gate pad located at the first surface, and a third electrode pad located at the first surface. A second chip is located on the first surface of the first chip. The second chip includes a third surface facing the first surface of the first chip, a fourth surface, a second semiconductor layer including a channel of a second conductivity type, a fourth electrode pad located at the fourth surface, a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first chip of a first type, the first chip including
a first surface,
a second surface at a side opposite to the first surface,
a first semiconductor layer including a nitride semiconductor layer of a first conductivity type,
a first electrode pad located at the first surface,
a second electrode pad located at the first surface,
a first gate pad located at the first surface, and
a third electrode pad located at the first surface; and

a second chip located on the first surface of the first chip, the second chip being of a second type that is different from the first type, the second chip including
a third surface facing the first surface of the first chip,
a fourth surface at a side opposite to the third surface,
a second semiconductor layer including a channel of a second conductivity type,
a fourth electrode pad located at the fourth surface,
a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and
a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.

2. The device according to claim 1 , further comprising:
a first gate terminal electrically connected to the first gate pad;
a power supply terminal electrically connected to the second electrode pad; and
a second gate terminal electrically connected to the third electrode pad,
the second electrode pad being positioned between the first gate pad and the third electrode pad in a first direction parallel to the first surface,
the power supply terminal being positioned between the first gate terminal and the second gate terminal in the first direction.

3. The device according to claim 1 , wherein
the first chip includes a HEMT (High Electron Mobility Transistor), and
the second chip includes a p-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

4. A semiconductor device, comprising:
a first chip of a first type, the first chip including
a first surface,
a second surface at a side opposite to the first surface,
a first semiconductor layer including a nitride semiconductor layer of a first conductivity type,
a first electrode pad located at the first surface,
a second electrode pad located at the first surface, and
a first gate pad located at the first surface; and

a second chip located on the first surface of the first chip, the second chip being of a second type that is different from the first type, the second chip including
a third surface facing the first surface of the first chip,
a fourth surface at a side opposite to the third surface,
a second semiconductor layer including a channel of a second conductivity type,
a third electrode pad located at the third surface and bonded to the second electrode pad of the first chip,
a second gate pad located at the third surface,
a fourth electrode pad located at the fourth surface,
a third gate pad located at the fourth surface, and
a connection member extending between the third surface and the fourth surface and electrically connecting the second gate pad and the third gate pad.

5. The device according to claim 4 , further comprising:
a first gate terminal electrically connected to the first gate pad;
a power supply terminal electrically connected to the second electrode pad; and
a second gate terminal electrically connected to the third gate pad,
the power supply terminal being positioned between the first gate terminal and the second gate terminal in a first direction parallel to the first surface.

6. The device according to claim 4 , wherein
the first chip includes a HEMT (High Electron Mobility Transistor), and
the second chip includes a p-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

7. A semiconductor device, comprising:
a first electrically conductive member including a first bonding portion;
a second electrically conductive member including a second bonding portion and a third bonding portion;
a third electrically conductive member including a fourth bonding portion;
a first chip of a first type;
a second chip of the first type;
a third chip located on the second bonding portion of the second electrically conductive member, the third chip being of a second type that is different from the first type; and
a fourth chip located on the fourth bonding portion of the third electrically conductive member, the fourth chip being of the second type,
the first chip and the second chip each including
a first surface,
a second surface at a side opposite to the first surface,
a first semiconductor layer including a nitride semiconductor layer of a first conductivity type,
a first electrode pad located at the first surface, and
a second electrode pad located at the first surface, the third chip and the fourth chip each including
a third surface facing the first surface,
a fourth surface at a side opposite to the third surface,
a second semiconductor layer including a channel of a second conductivity type,
a third electrode pad located at the fourth surface, and
a fourth electrode pad located at the third surface,

the first electrode pad of the first chip being bonded to the first bonding portion of the first electrically conductive member,
the third electrode pad of the third chip being bonded to the second bonding portion of the second electrically conductive member,
the second electrode pad of the first chip being bonded to the fourth electrode pad of the third chip,
the first electrode pad of the second chip being bonded to the third bonding portion of the second electrically conductive member,
the third electrode pad of the fourth chip being bonded to the fourth bonding portion of the third electrically conductive member,
the second electrode pad of the second chip being bonded to the fourth electrode pad of the fourth chip.

8. The device according to claim 7 , further comprising:
a heat dissipation member located on the second surface of the first chip and on the second surface of the second chip.

9. The device according to claim 7 , further comprising:
a fourth electrically conductive member,
the third chip and the fourth chip each further including a gate pad located at the third surface,
the gate pad being electrically connected to the fourth electrically conductive member by a wire.

10. The device according to claim 7 , wherein
the first chip and the second chip include a HEMT (High Electron Mobility Transistor), and
the third chip and the fourth chip include a p-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor).

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Sugiyama Toru
• Yoshioka Akira
• Isobe Yasuhiro

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/481 Primary

  for devices being provided for in groups H10D8/00 - H10D48/00 · CPC title

• H10W70/465

  Bumps or wires · CPC title

• H10W70/461

  specially adapted for cooling · CPC title