Efficient high voltage switching circuits and monolithic integration of same
US-9219058-B2 · Dec 22, 2015 · US
Cascode circuit integration of group III-N and group IV devices
US9202811B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9202811-B2 |
| Application number | US-201314073783-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 6, 2013 |
| Priority date | Dec 18, 2012 |
| Publication date | Dec 1, 2015 |
| Grant date | Dec 1, 2015 |
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Abstract
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In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board. At least one via in the printed circuit board electrically connects the depletion mode III-Nitride transistor die to the group IV transistor die. In some implementations, the depletion mode III-Nitride transistor die is in cascode with the group IV transistor die. Furthermore, the depletion mode III-Nitride transistor die can be situated over the group IV transistor die.
First claim
Opening claim text (preview).
The invention claimed is: 1. An integrated assembly comprising: a printed circuit board; a depletion mode III-Nitride transistor die and a group IV transistor die coupled to said printed circuit board; said depletion mode HI-Nitride transistor die situated on one side of said printed circuit board and said group IV transistor die situated on an opposing side of said printed circuit board; at least one via in said printed circuit board electrically connecting said depletion…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9202811B2 cover?
- In an exemplary implementation, an integrated assembly includes a printed circuit board, and a depletion mode III-Nitride transistor die and a group IV transistor die coupled to the printed circuit board. The depletion mode III-Nitride transistor die is situated on one side of the printed circuit board and the group IV transistor die is situated on an opposing side of the printed circuit board.…
- Who is the assignee on this patent?
- Int Rectifier Corp, Infineon Technologies Americas Corp
- What technology area does this patent fall under?
- Primary CPC classification H10D84/84. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).