Group III-V and group IV composite switch

Patent metadata

Field	Value
Publication number	US-9362267-B2
Application number	US-201313780436-A
Country	US
Kind code	B2
Filing date	Feb 28, 2013
Priority date	Mar 15, 2012
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

In one implementation, a group III-V and group IV composite switch includes a group IV transistor in a lower active die, the group IV transistor having a source and a gate situated on a bottom side of the lower active die. The group III-V and group IV composite switch also includes a group III-V transistor in an upper active die stacked over the lower active die, the group III-V transistor having a drain, a source, and a gate situated on a top side of the upper active die. The source of the group III-V transistor is electrically coupled to a drain of the group IV transistor using a through-semiconductor via (TSV) of the upper active die.

First claim

The invention claimed is:

1. A composite switch comprising:
a group IV transistor in a lower active die, a source and a gate of said group IV transistor being situated on a bottom side of said lower active die;
a group III-V transistor in an upper active die stacked over said lower active die, a drain, a source, and a gate of said group III-V transistor being situated on a top side of said upper active die;
said source of said group III-V transistor being electrically coupled to a drain of said group IV transistor using a through-semiconductor via (TSV) of said upper active die;
a source contact of said group III-V transistor formed directly on top of a drain of said group IV transistor.

2. The composite switch of claim 1 , wherein said group IV transistor is a vertical group IV transistor.

3. The composite switch of claim 1 , wherein said TSV does not reach a bottom side of said upper active die.

4. The composite switch of claim 3 , wherein said TSV reaches a highly conductive substrate in said upper active die, said highly conductive substrate being in electrical contact with said drain of said group IV transistor.

5. The composite switch of claim 1 , wherein said TSV reaches a bottom side of said upper active die.

6. The composite switch of claim 1 , wherein said group III-V transistor is a normally ON transistor and said composite switch is configured to be normally OFF.

7. The composite switch of claim 1 , wherein said group III-V transistor is a high-voltage (HV) transistor and said group IV transistor is a low-voltage (LV) transistor.

8. The composite switch of claim 1 , wherein said group III-V transistor is a III-Nitride high electron mobility transistor (III-Nitride HEMT).

9. The composite switch of claim 1 , wherein said group transistor comprises gallium nitride (GaN).

10. The composite switch of claim 1 , wherein said group IV transistor comprises silicon.

Assignees

• Int Rectifier Corp
• Infineon Technologies Americas Corp

Inventors

• Briere Michael A
• Mcdonald Tim

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10D84/00 Primary

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title