Plurality of leads between MOSFET chips

Patent metadata

Field	Value
Publication number	US-11594476-B2
Application number	US-202117201544-A
Country	US
Kind code	B2
Filing date	Mar 15, 2021
Priority date	Sep 15, 2020
Publication date	Feb 28, 2023
Grant date	Feb 28, 2023

Abstract

A semiconductor device includes: a first chip including first and second electrodes provided at a first surface, and a third electrode provided at a second surface positioned at a side opposite to the first surface; a second chip including fourth and fifth electrodes provided at a third surface, and a sixth electrode provided at a fourth surface positioned at a side opposite to the third surface, wherein the second chip is disposed to cause the third surface to face the first surface; a first connector disposed between the first electrode and the fourth electrode and connected to the first and fourth electrodes; and a second connector disposed between the second electrode and the fifth electrode and connected to the second and fifth electrodes.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first chip including
a first source electrode and a first gate electrode provided at a first surface of the first chip, and
a first drain electrode provided at a second surface of the first chip, the second surface being positioned at a side opposite to the first surface;

a second chip including
a second source and a second gate electrode provided at a third surface of the second chip, the second chip being disposed to cause the third surface to face the first surface, and
a second drain electrode provided at a fourth surface of the second chip, the fourth surface being positioned at a side opposite to the third surface;

a first connector disposed between the first chip and the second chip and connected to the first source electrode and the second source electrode; and
a second connector disposed between the first chip and the second chip and connected to the first gate electrode and the second gate electrode.

2. The device according to claim 1 , further comprising:
a substrate connected to the first drain electrode and disposed to face the second surface of the first chip; and
a third connector connected to the substrate and the second drain electrode of the second chip.

3. The device according to claim 2 , wherein
the first connector comprises a first part facing a first side surface of the first chip, and
the third connector comprises a third part facing a second side surface of the first chip.

4. The device according to claim 3 , wherein
the second connector comprises a second part facing the first side surface of the first chip.

5. The device according to claim 3 , wherein
the first side surface is connected to the second side surface, and
the first side surface is in non-parallel to the second side surface.

6. The device according to claim 2 , wherein
the second surface is closer to the substrate than the first surface, and the third surface is closer to the substrate than the fourth surface.

7. The device according to claim 1 , wherein
the first connector includes a first distal part positioned between the first source electrode and the second source electrode,
the first distal part includes:
a first portion; and
a second portion provided at a periphery of the first portion,

a distance between the second portion and the first source electrode is less than a distance between the first portion and the first source electrode, and
a distance between the second portion and the second source electrode is greater than a distance between the first portion and the second source electrode.

8. The device according to claim 1 , wherein
the first connector includes a first distal part positioned between the first source electrode and the second source electrode, and
the first distal part has a wave-like shape.

9. The device according to claim 1 , wherein
the first connector includes a first distal part positioned between the first source electrode and the second source electrode, and
the first distal part includes a protrusion protruding toward the first source electrode or the second source electrode.

10. The device according to claim 1 , wherein
the second connector includes a second distal part positioned between the first gate electrode and the second gate electrode, and
the second distal part includes a curved portion.

11. The device according to claim 1 , wherein
the first source electrode and the first gate electrode are in direct contact with the first surface, and the first drain electrode is in direct contact with the second surface, and
the second source electrode and the second gate electrode are in direct contact with the third surface, and the second drain electrode is in direct contact with the fourth surface.

12. A semiconductor device, comprising:
a first chip including
a first source electrode and a first gate electrode provided at a first surface of the first chip, and
a first drain electrode provided at a second surface of the first chip, the second surface being positioned at a side opposite to the first surface;

a second chip including
a second source and a second gate electrode provided at a third surface of the second chip, and
a second drain electrode provided at a fourth surface of the second chip, the fourth surface being positioned at a side opposite to the third surface, the second chip being disposed to cause the fourth surface to face the second surface; and

a first connector disposed between the first drain electrode and the second drain electrode and connected to the first drain electrode and the second drain electrode.

13. The device according to claim 12 , further comprising:
a substrate disposed to face the first surface of the first chip, the substrate including
a first interconnect connected to the first source electrode, and
a second interconnect connected to the first gate electrode;

a second connector connected to the first interconnect and the second source electrode of the second chip; and
a third connector connected to the second interconnect and the second gate electrode of the second chip.

14. The device according to claim 13 , wherein
the first surface is closer to the substrate than the second surface, and
the fourth surface is closer to the substrate than the third surface.

15. The device according to claim 12 , wherein
the first connector includes a distal part positioned between the first drain electrode and the second drain electrode,
the distal part includes:
a first portion; and
a second portion provided at a periphery of the first portion,

a distance between the second portion and the first drain electrode is less than a distance between the first portion and the first drain electrode, and
a distance between the second portion and the second drain electrode is greater than a distance between the first portion and the second drain electrode.

16. The device according to claim 12 , wherein
the first connector includes a distal part positioned between the first drain electrode and the second drain electrode, and
the distal part has a wave-like shape.

17. The device according to claim 12 , wherein
the first connector includes a distal part positioned between the first drain electrode and the second drain electrode, and
the distal part includes a protrusion protruding toward the first drain electrode or the second drain electrode.

18. The device according to claim 12 , wherein
the first drain electrode is in direct contact with the second surface, and
the second drain electrode is in direct contact with the fourth surface.

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Ohguro Tatsuya
• Kojima Hideharu

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/07653

  changes in shapes · CPC title

• H10W72/631

  Shapes of strap connectors · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W72/60

  Strap connectors, e.g. thick copper clips for grounding of power devices · CPC title