Systems and methods for improving within die co-planarity uniformity

Patent metadata

Field	Value
Publication number	US-11984358-B2
Application number	US-202217742962-A
Country	US
Kind code	B2
Filing date	May 12, 2022
Priority date	Sep 20, 2018
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

Exemplary methods of producing a semiconductor substrate may include plating a metal within a plurality of vias on the semiconductor substrate. A target average fill thickness of the metal within the plurality of vias may be between about a thickness equal to an average via radius of the plurality of vias and a thickness twice the average via radius of the plurality of vias. At least one via of the plurality of vias may be filled to a height below the target average fill thickness of the metal. The methods may include heating the metal to cause reflow of the metal within each via of the plurality of vias. The reflow may adjust the metal within the at least one via to increase in height towards the target average fill thickness.

First claim

What is claimed is:

1. A method of filling vias in a semiconductor substrate, the method comprising:
plating a metal within a plurality of vias on the semiconductor substrate, wherein a target average fill thickness of the metal within the plurality of vias is between about a thickness equal to an average via radius of the plurality of vias and a thickness twice the average via radius of the plurality of vias, wherein at least one via of the plurality of vias is filled to a height below the target average fill thickness of the metal, and wherein a second via of the plurality of vias separate from the at least one via and having the metal within the at least one via filled to a height above the target average fill thickness of the metal; and
heating the metal to cause reflow of the metal within each via of the plurality of vias, wherein the reflow adjusts the metal within the at least one via to increase in height towards the target average fill thickness, and wherein the reflow adjusts the metal within the second via to decrease in height towards the target average fill thickness of the metal.

2. The method of filling vias in a semiconductor substrate of claim 1 , wherein the target average fill thickness of the metal within the plurality of vias is about equal to the average via radius of the plurality of vias times about 1.5 to about 2.

3. The method of filling vias in a semiconductor substrate of claim 1 , wherein the metal is a first metal and wherein the first metal is formed overlying a second metal within each via of the plurality of vias.

4. The method of filling vias in a semiconductor substrate of claim 3 , wherein the first metal is characterized by a melting point below or about 200° C.

5. The method of filling vias in a semiconductor substrate of claim 3 , wherein the first metal comprises tin silver, and wherein the second metal comprises one or more metals selected from the group consisting of copper, cobalt, nickel, and tungsten.

6. The method of filling vias in a semiconductor substrate of claim 5 , further comprising a third metal formed within each via of the plurality of vias, wherein the second metal comprises copper, and wherein the third metal comprises nickel.

7. The method of filling vias in a semiconductor substrate of claim 1 , wherein adjusting the metal within the at least one via of the plurality of vias comprises modifying a geometry of the metal within the at least one via of the plurality of vias.

8. The method of filling vias in a semiconductor substrate of claim 7 , wherein the metal is characterized by a pre-reflow cylindrical geometry and wherein the metal is characterized by a post-reflow hemispherical geometry.

9. A method of producing a semiconductor substrate, the method comprising:
characterizing a substrate pattern to identify a zonal distribution of a plurality of vias and a height and a radius of each via of the plurality of vias;
determining a fill rate for each via within the zonal distribution of the plurality of vias;
modifying a die pattern to adjust via fill rates between two zones of vias;
producing a semiconductor substrate according to the die pattern;
plating a metal within the plurality of vias on the semiconductor substrate produced, wherein a target average fill thickness of the metal within the plurality of vias is between about a thickness equal to an average via radius of the plurality of vias and a thickness twice the average via radius of the plurality of vias, wherein at least one via of the plurality of vias is filled to a height below the target average fill thickness of the metal, and wherein a second via of the plurality of vias separate from the at least one via and having the metal within the at least one via filled to a height above the target average fill thickness of the metal; and
heating the metal to cause reflow of the metal within each via of the plurality of vias, wherein the reflow adjusts the metal within the at least one via to increase in height towards the target average fill thickness, and wherein the reflow adjusts the metal within the second via to decrease in height towards the target average fill thickness of the metal.

10. The method of producing a semiconductor substrate of claim 9 , wherein, subsequent the reflow, a total fill height of metal within each via of the plurality of vias is within 5% of an average total fill height of metal within each via of the plurality of vias.

11. A method of filling vias in a semiconductor substrate, the method comprising:
producing a semiconductor substrate according to a die pattern;
plating a metal within a plurality of vias on the semiconductor substrate, wherein a target average fill thickness of the metal within the plurality of vias is between about a thickness equal to an average via radius of the plurality of vias and a thickness twice the average via radius of the plurality of vias, at least one via of the plurality of vias is filled to a height below the target average fill thickness of the metal, wherein a second via of the plurality of vias separate from the at least one via and having the metal within the at least one via filled to a height above the target average fill thickness of the metal; and
heating the metal to cause reflow of the metal within each via of the plurality of vias, wherein the reflow adjusts the metal within the at least one via to increase in height towards the target average fill thickness, and wherein the reflow adjusts the metal within the second via to decrease in height towards the target average fill thickness of the metal.

12. The method of filling vias in a semiconductor substrate of claim 11 , wherein the reflow adjusts the metal within the at least one via to increase in height towards the target average fill thickness.

13. The method of filling vias in a semiconductor substrate of claim 11 , wherein the target average fill thickness of the metal within the plurality of vias is about equal to the average via radius of the plurality of vias times about 1.5 to about 2.

14. The method of filling vias in a semiconductor substrate of claim 11 , further comprising:
modifying the die pattern to adjust via fill rates between two zones of vias.

15. The method of filling vias in a semiconductor substrate of claim 11 , wherein the metal is a first metal and wherein the first metal is formed overlying a second metal within each via of the plurality of vias.

16. The method of filling vias in a semiconductor substrate of claim 15 , wherein the first metal comprises tin silver, and wherein the second metal comprises one or more metals selected from the group consisting of copper, cobalt, nickel, and tungsten.

17. The method of filling vias in a semiconductor substrate of claim 15 , further comprising a third metal formed within each via of the plurality of vias, wherein the first metal comprises tin silver, wherein the second metal comprises copper, and wherein the third metal comprises nickel.

18. The method of filling vias in a semiconductor substrate of claim 11 , subsequent the reflow, a total fill height of metal within each via of the plurality of vias is within 5% of an average total fill height of metal within each via of the plurality of vias.

Assignees

• Applied Materials Inc

Inventors

• Mchugh Paul
• Roh Kwan Wook
• Wilson Gregory J

Classifications

• H10P14/47

  Electrolytic deposition, i.e. electroplating; Electroless plating · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056 Primary

  by filling conductive material into holes, grooves or trenches · CPC title

• H01L21/76883 Primary

  Electricity · mapped topic