Multiple-patterned semiconductor device channels

Patent metadata

Field	Value
Publication number	US-9252100-B2
Application number	US-201313836335-A
Country	US
Kind code	B2
Filing date	Mar 15, 2013
Priority date	Mar 12, 2013
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A semiconductor device and method of manufacture are provided. The semiconductor device may include a multiple-patterned layer which may include multiple channels defined by multiple masks. A width of a first channel may be smaller than a width of a second channel. A conductor in the first channel may have a conductor width substantially equivalent to a conductor width of a conductor in the second channel. A spacer dielectric on a channel side may be included. The method of manufacture includes establishing a signal conductor layer including channels defined masks where a first channel may have a first width smaller than a second width of a second channel, introducing a spacer dielectric on a channel side, introducing a first conductor in the first channel having a first conductor width, and introducing a second conductor in the second channel having a second conductor width substantially equivalent to the first conductor width.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
establishing a signal conductor layer formed of an insulator, the signal conductor layer having adjacent channels for wiring tracks, the adjacent channels including:
a first channel defined by a first mask having a design width and a second channel defined by a second mask having the design width, the first channel processed having a first width and the second channel processed having a second width, the first width smaller than the second width, a difference between the first width and the second width caused by tracking;

introducing a spacer dielectric on a side of the second channel, the spacer dielectric touching the insulator and bordered on at least two edges by the insulator;
introducing a first conductor in the first channel having a first conductor width, the first conductor touching the insulator and bordered on at least three edges by the insulator; and
introducing a second conductor in the second channel having a second conductor width, the second conductor touching the insulator and touching the spacer dielectric, the second conductor bordered on at least one edge by the insulator, the first conductor width substantially equivalent to the second conductor width.

2. The method of claim 1 , wherein the side is a vertical side.

3. The method of claim 2 , wherein the spacer dielectric has a permittivity less than 3.0.

4. The method of claim 2 , wherein the spacer dielectric has a total width substantially equivalent to the difference between the second width and the first width.

5. A method of manufacturing a semiconductor device, comprising:
establishing a signal conductor layer formed of an insulator, the signal conductor layer having adjacent trenches for wiring tracks, the adjacent trenches including:
defining a first portion of the signal conductor layer with a first mask and defining a second portion of the signal conductor layer with a second mask the first mask having a first pattern, including a design width, for a first trench and the second mask having a second pattern, including the design width, for a second trench, the first trench processed having a first trench width and the second trench processed having a second trench width, the first trench width smaller than the second trench width, a difference between the first trench width and the second trench width caused by tracking;

introducing a spacer dielectric material to the second trench, the first trench not including the spacer dielectric material;
introducing a photoresist material to at least one of the signal conductor layer and the spacer dielectric material;
exposing at least a portion of at least one of the spacer dielectric material and the photoresist material;
removing a first portion of the spacer dielectric material and retaining a second portion of the spacer dielectric material, the second portion of the spacer dielectric material having a thickness substantially equivalent to half the difference of the first trench width and the second trench width;
removing the photoresist material; and
introducing a conductive material to the signal conductor layer wherein a first conductive material width associated with the first trench is substantially equivalent to a second conductive material width associated with the second trench, the first conductive material bordered on at least three edges by the insulator.

6. The method of claim 5 , wherein introducing the spacer dielectric material includes blanket depositing the spacer dielectric material.

7. The method of claim 5 , wherein removing the first portion of the spacer dielectric material includes wet etching the portion of the spacer dielectric material exposed.

8. The method of claim 5 , wherein removing the first portion of the spacer dielectric material and retaining the second portion of the spacer dielectric material includes anisotropically etching the spacer dielectric material except for that which exists as a spacer on a side of the second trench.

9. The method of claim 5 , wherein removing the photoresist material includes plasma ashing the photoresist material.

10. The method of claim 5 , wherein exposing at least the portion of the photoresist material includes at least one of developing the photoresist material and hardening undeveloped photoresist material.

11. The method of claim 5 , wherein exposing at least the portion of at least one of the spacer dielectric material and the photoresist material includes exposing at least a width of at least one of the first trench and the second trench.

Assignees

• IBM

Inventors

• Allen David H
• Dewanz Douglas M
• Paulsen David P
• Sheets Ii John E
• Williams Kelly L

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title