Method of forming masks

Patent metadata

Field	Value
Publication number	US-2016283631-A1
Application number	US-201614995413-A
Country	US
Kind code	A1
Filing date	Jan 14, 2016
Priority date	Feb 12, 2015
Publication date	Sep 29, 2016
Grant date	—

Abstract

A method of forming a set of masks for manufacturing an integrated circuit includes determining a presence of a first via layout pattern and a power rail layout pattern in an original layout design. The first via layout pattern and the power rail layout pattern overlap each other. The first via layout pattern is part of a first cell layout of the original layout design. The power rail layout pattern is shared by the first cell layout and a second cell layout of the original layout design. The method further includes modifying the original layout design to become a modified layout design and forming the set of masks based on the modified layout design. The modifying the original layout design includes, if the first via layout pattern and the power rail are present in the original layout design, replacing the first via layout pattern with an enlarged via layout pattern.

First claim

What is claimed is:

1 . A method of forming a set of masks for manufacturing an integrated circuit, the method comprising:
determining a presence of a first via layout pattern and a power rail layout pattern in an original layout design, the first via layout pattern and the power rail layout pattern overlapping each other, the first via layout pattern being part of a first cell layout of the original layout design, the power rail layout pattern being shared by the first cell layout and a second cell layout of the original layout design and extending along a cell boundary between the first cell layout and the second cell layout, the first via layout pattern corresponding to a first via plug layer of the integrated circuit, and the shared power rail layout pattern corresponding to a first conductive layer of the integrated circuit above the first via plug layer; and modifying the original layout design to result in a modified layout design, comprising:
if the first via layout pattern and the power rail are present in the original layout design, replacing the first via layout pattern with an enlarged via layout pattern, the enlarged via layout pattern occupying an area greater than that occupied by the first via layout pattern; and
forming the set of masks based on the modified layout design.

2 . The method of claim 1 , further comprising:
determining a presence of a second via layout pattern in the original layout design, the second via layout pattern and the power rail layout pattern overlapping each other, the second via layout pattern being part of the second cell layout, wherein the modifying the original layout design further comprises:
if the second via layout pattern is present in the original layout pattern, replacing the second via layout pattern with the enlarged via layout pattern, the enlarged via layout pattern overlapping the cell boundary between the first cell layout and the second cell layout.

3 . The method of claim 2 , wherein
the first cell layout of the original layout design further comprises a first conductive layout pattern corresponding to a second conductive layer of the integrated circuit, the second conductive layer being below the first via plug layer; the second cell layout of the original layout design further comprises a second conductive layout pattern corresponding to the second conductive layer of the integrated circuit; and the modifying the original layout design further comprises:
generating a merged conductive layout pattern based on the first conductive layout pattern and the second conductive layout pattern, the merged conductive layout pattern corresponding to the second conductive layer; and
replacing the first conductive layout pattern and the second conductive layout pattern with the merged conductive layout pattern, the enlarged via layout pattern overlapping the merged conductive layout pattern.

4 . The method of claim 2 , wherein
the first cell layout of the original layout design further comprises a first conductive layout pattern corresponding to a second conductive layer of the integrated circuit, the second conductive layer being below the first via plug layer; the second cell layout of the original layout design further comprises a second conductive layout pattern corresponding to a third conductive layer of the integrated circuit, the third conductive layer being below the first via plug layer, the second conductive layer and the third conductive layer having different thicknesses; and the modifying the original layout design further comprises:
generating a modified first conductive layout pattern based on the first conductive layout pattern, the modified first conductive layout pattern corresponding to the second conductive layer, and the enlarged via layout pattern overlapping the modified first conductive layout pattern and the second conductive layout pattern; and
replacing the first conductive layout pattern with the modified first conductive layout pattern.

5 . The method of claim 4 , wherein generating the modified first conductive layout pattern comprises reshaping or shifting the first conductive layout pattern such that an edge of the modified first conductive layout pattern, in comparison with a corresponding edge of the first conductive layout pattern, is shifted toward the cell boundary between the first cell layout and the second cell layout.

6 . The method of claim 2 , wherein
the first cell layout of the original layout design further comprises a first conductive layout pattern corresponding to a second conductive layer of the integrated circuit, the second conductive layer being below the first via plug layer; the second cell layout of the original layout design further comprises a second conductive layout pattern corresponding to a third conductive layer of the integrated circuit, the third conductive layer being below the first via plug layer, the second conductive layer and the third conductive layer having different thicknesses; and the modifying the original layout design further comprises:
generating a modified first conductive layout pattern based on the first conductive layout pattern, the modified first conductive layout pattern corresponding to the second conductive layer, and the enlarged via layout pattern overlapping the modified first conductive layout pattern;
generating a modified second conductive layout pattern based on the second conductive layout pattern, the modified second conductive layout pattern corresponding to the third conductive layer, and the enlarged via layout pattern overlapping the modified second conductive layout pattern;
replacing the first conductive layout pattern with the modified first conductive layout pattern; and
replacing the second conductive layout pattern with the modified second conductive layout pattern.

7 . The method of claim 1 , wherein replacing the first via layout pattern with an enlarged via layout pattern comprises applying a ratio of the area occupied by the enlarged via layout pattern to the area occupied by the first via layout pattern based on at least one of a minimum performance improvement or a minimum spacing layout rule.

8 . The method of claim 7 , wherein the ratio ranges from 2.25 to 2.89.

9 . A method of forming a set of masks for manufacturing an integrated circuit, the method comprising:
determining a presence of a first conductive layout pattern, a first via layout pattern overlapping the first conductive layout pattern, a second conductive layout pattern, a second via layout pattern overlapping the second conductive layout pattern, and a power rail layout pattern in an original layout design, the power rail layout pattern overlapping the first conductive layout pattern, the first via layout pattern, the second conductive layout pattern, and the second via layout pattern, the first via layout pattern and the first conductive layout pattern being part of a first cell layout of the original layout design, the second via layout pattern and the second conductive layout pattern being part of a second cell layout of the original layout design, the power rail layout pattern being shared by the first cell layout and the second cell layout and extending along a cell boundary between the first cell layout and the second cell layout, the first conductive layout pattern and the second conductive layout pattern being aligned along a direction perpendicular to the cell boundary between the first cell layout and the second cell layout; modifying the original layout design to result in a modified layout design, comprising:
if the first conductive layout pattern, the first via layout pattern, the second conductive layout pattern, the second via layout pattern, and the p

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Yi-Hsiung
• Guo Ta-Pen
• Chiu Yi-Hsun

Classifications

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• H10W20/427

  Power or ground buses · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/0698 Primary

  Local interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title