Efficient deconfiguration of a reconfigurable data processor

Patent metadata

Field	Value
Publication number	US-11983140-B2
Application number	US-202117533058-A
Country	US
Kind code	B2
Filing date	Nov 22, 2021
Priority date	Nov 21, 2018
Publication date	May 14, 2024
Grant date	May 14, 2024

Abstract

A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. A configuration unload controller connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to a plurality of the configurable units in the array to unload the unit files particular to the corresponding configurable units, the unit files each comprising a plurality of ordered sub-files, receiving sub-files via the bus system from the array of configurable units, and assembling an unload configuration file by arranging the received sub-files in memory according to the configurable unit of the unit file of which the sub-file is a part, and the order of the sub-file in the unit file.

First claim

What is claimed is:

1. A reconfigurable data processor, comprising:
a bus system;
an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to corresponding configurable units; and
a configuration unload controller connected to the bus system, including logic to execute an array configuration unload process, including distributing a command to a plurality of the configurable units in the array to unload the unit files particular to the corresponding configurable units, the unit files each comprising a plurality of ordered sub-files, receiving sub-files via the bus system from the array of configurable units, and assembling an unload configuration file by arranging the received sub-files in memory according to the configurable unit of the unit file of which the sub-file is a part, and the order of the sub-file in the unit file.

2. The processor of claim 1 , wherein configurable units in the plurality of configurable units each include logic to execute a unit configuration unload process, including unloading the sub-files from the configuration store of the configurable unit and transmitting via the bus system, sub-files of a unit file particular to the configurable unit to the configuration unload controller.

3. The processor of claim 2 , wherein the configuration data store in a configurable
unit in the plurality of configurable units comprises a serial chain and an output buffer coupled to the serial chain, and the unit configuration unload process shifts the sub-files of the unit file out of the serial chain to the output buffer, and transmits the sub-file from the output buffer on the bus system.

4. The processor of claim 1 , wherein the array configuration unload process includes
receiving from a host process, configuration unload command identifying an address location in memory at which to store an unload configuration file, and said assembling includes calculating address offsets from the address location for the sub-files.

5. The processor of claim 1 , wherein the configuration file includes a plurality of sub-files of unit files for each configurable unit in a plurality of configurable units, the unit files having up to M sub-files having an order (i) in the unit file, and being arranged in the unload configuration file so that all sub-files of order (i) for all the unit files in the unload configuration file are stored in a corresponding block (i) of address space in the memory, for (i) going from O to M-1.

6. The processor of claim 5 , wherein the array includes more than one type of configurable unit, and the unit files for different types of configurable units include different numbers of sub-files of configuration data, and wherein within a block (i) of address space, the sub-files for each type of configurable unit are stored in a group of contiguous addresses within the block (i).

7. The processor of claim 1 , wherein a sub-file has a number N of bits of data, and
the bus system is configured to transfer N bits of data in one bus cycle.

8. The processor of claim 1 , wherein the unit files of the configurable units in the
array of configurable units have at most M sub-files, and said arranging the received subfiles in memory includes:
storing the unload configuration file in memory in a plurality of blocks (i) of addresses, for (i) going from Oto up to M- 1 , and storing sub-file (i), of the unit files for all of the configurable units in the plurality of configurable units in block (i); and
transmitting said sub-files includes sending packets on the bus system having a header and a payload, the payload including the sub-files, and the header identifying the configurable unit from with the sub-file is being sent and the order of the sub-file.

9. The processor of claim 1 , wherein the bus system includes a top level network
including an external data interface and an array interface, and an array level network connected to the array interface and to the configurable units in the array of configurable units.

10. The processor of claim 9 , wherein the array configuration unload process routes
sub-files of the unload configuration file to memory via the top level network using addresses implied by order of the sub-files in the unit files of the configurable units.

11. The processor of claim 9 , wherein the unit configuration unload process routes
sub-files of the unload configuration file to memory via the top level network using addresses implied by order of the sub-files in the unit files of the configurable units.

12. The processor of claim 1 , wherein configurable units in the plurality of configurable units use routes in the bus system during execution before unloading the configuration file also used in the configuration unload process.

13. The processor of claim 1 , wherein the unit files comprise a plurality of ordered
sub-files, and the unload configuration file for an array of configurable units is assembled so that sub-files of the same order for all the configurable units of the same type are stored in a block of address space, and so that location of a sub-file in the unload configuration file corresponds with the configurable unit in the array of the sub-file and its order in the unit file particular to the configurable unit.

14. A method for operating a reconfigurable data processor comprising a bus system
and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of subfiles
of configuration data particular to the corresponding configurable units, the method comprising:
distributing a command to a plurality of the configurable units in the array to unload the unit files particular to the corresponding configurable units, the unit files each comprising a plurality of ordered sub-files.

15. The method of claim 14 , including receiving sub-files from the array of
configurable units from the bus system and assembling an unload configuration file by arranging the received sub-files in memory according to the configurable unit of the unit file of which the sub-file is a part, and the order of the sub-file in the unit file.

16. The method of claim 15 , wherein the configuration file includes a plurality of subfiles
of unit files for each configurable unit in a plurality of configurable units, the unit files having up to M sub-files having an order (i) in the unit file, and being arranged in the unload configuration file so that all sub-files of order (i) for all the unit files in the unload configuration file are stored in a corresponding block (i) of address space in the memory, for (i) going from O to M-1.

17. The method of claim 16 , wherein the array includes more than one type of configurable unit, and the unit files for different types of configurable units include different numbers of sub-files of configuration data, and wherein within a block (i) of address space, the sub-files for each type of configurable unit are stored in a group of contiguous addresses within the block (i) of address space.

18. The method of claim 14 , including unloading the sub-files from the configuration
store of the configurable unit and transmitting via the bus system, sub-files of a unit file particular to the configurable unit to the configuration unload controller.

19. The method of claim 14 , wherein the configuration data store in a co

Assignees

• Sambanova Systems Inc

Inventors

• Shah Manish K
• Sivaramakrishnan Ram
• Luttrell Mark
• Jackson David B
• Prabhakar Raghu
• Jairath Sumti
• Grohoski Gregory Frederick
• Nataraja Pramod

Classifications

• G06F15/7871 Primary

  Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS · CPC title

• G06F9/44505

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• G06F8/65

  Updates (security arrangements therefor G06F21/57) · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title