Vector processing engines having programmable data path configurations for providing multi-mode vector processing, and related vector processors, systems, and methods

Patent metadata

Field	Value
Publication number	US-9495154-B2
Application number	US-201313798641-A
Country	US
Kind code	B2
Filing date	Mar 13, 2013
Priority date	Mar 13, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

Embodiments disclosed herein include vector processing engines (VPEs) having programmable data path configurations for providing multi-mode vector processing. Related vector processors, systems, and methods are also disclosed. The VPEs include a vector processing stage(s) configured to process vector data according to a vector instruction executed in the vector processing stage. Each vector processing stage includes vector processing blocks each configured to process vector data based on the vector instruction being executed. The vector processing blocks are capable of providing different vector operations for different types of vector instructions based on data path configurations. Data paths of the vector processing blocks are programmable to be reprogrammable to process vector data differently according to the particular vector instruction being executed. In this manner, a VPE can be provided with its data paths configuration programmable to execute different types of functions based on data path configuration according to the vector instruction being executed.

First claim

What is claimed is:

1. A vector processing engine (VPE) configured to provide multi-mode vector processing of vector data, comprising:
an input read stage configured to provide a plurality of vector data input sample sets in a plurality of input data paths;
at least one vector processing stage comprising a plurality of vector processing blocks, each vector processing block among the plurality of vector processing blocks configured to:
receive at least two vector data input sample sets from the plurality of vector data input sample sets from at least two input data paths among the plurality of input data paths;
process the at least two vector data input sample sets to provide at least one vector result output sample set based on a programmable data path configuration for the vector processing block according to a vector instruction executed by the at least one vector processing stage, wherein the vector processing block comprises a plurality of multipliers, the processing by the vector processing block comprises performing a first multiplication operation on the at least two vector data input sample sets using the plurality of multipliers in a first configuration, the programmable data path configuration is configured to be reconfigured to reconfigure the plurality of multipliers into a second configuration to perform a second multiplication operation, and the first multiplication operation and the second multiplication operation are different bit length multiplication operations; and
provide the at least one vector result output sample set in at least one output data path among a plurality of output data paths; and

an output processing stage configured to receive the at least one vector result output sample set from each of the plurality of vector processing blocks.

2. The VPE of claim 1 , wherein the programmable data path configuration for each of the plurality of vector processing blocks is configured to be reconfigured for each vector instruction executed by the at least one vector processing stage.

3. The VPE of claim 1 , wherein the programmable data path configuration for each of the plurality of vector processing blocks is configured to be reconfigured on each clock cycle of the vector instruction executed by the at least one vector processing stage.

4. The VPE of claim 1 , wherein:
the programmable data path configuration for each of the plurality of vector processing blocks is comprised of a programmable input data path configuration; and
each of the plurality of vector processing blocks is configured to receive the at least two vector data input sample sets from the at least two input data paths among the plurality of input data paths based on the programmable input data path configuration according to the vector instruction executed by the at least one vector processing stage.

5. The VPE of claim 4 , wherein:
the programmable data path configuration for each of the plurality of vector processing blocks is further comprised of a programmable output data path configuration for the at least one vector processing block; and
each of the plurality of vector processing blocks is configured to provide the at least one vector result output sample set in the at least one output data path among the plurality of output data paths based on the programmable output data path configuration according to the vector instruction executed by the at least one vector processing stage.

6. The VPE of claim 5 , wherein:
the programmable data path configuration for each of the plurality of vector processing blocks is further comprised of a programmable vector processing block data path configuration for the at least one vector processing block; and
each of the plurality of vector processing blocks is configured to process the at least two vector data input sample sets to provide the at least one vector result output sample set based on the programmable vector processing block data path configuration according to the vector instruction executed by the at least one vector processing stage.

7. The VPE of claim 1 , wherein:
the programmable data path configuration for each of the plurality of vector processing blocks is comprised of a programmable output data path configuration for the at least one vector processing block; and
each of the plurality of vector processing blocks is configured to provide the at least one vector result output sample set in the at least one output data path among the plurality of output data paths based on the programmable output data path configuration according to the vector instruction executed by the at least one vector processing stage.

8. The VPE of claim 1 , wherein:
the programmable data path configuration for each of the plurality of vector processing blocks is comprised of a programmable vector processing block data path configuration for the at least one vector processing block; and
each of the plurality of vector processing blocks is configured to process the at least two vector data input sample sets to provide the at least one vector result output sample set based on the programmable vector processing block data path configuration according to the vector instruction executed by the at least one vector processing stage.

9. The VPE of claim 1 , wherein the at least one vector processing block is comprised of at least one of: at least one multiplier block and at least one accumulator block.

10. The VPE of claim 1 , wherein the at least one vector processing stage is comprised of a plurality of vector processing stages.

11. The VPE of claim 1 , wherein the at least one vector processing stage is comprised of at least one multiply vector processing stage comprised of a plurality of multiplier blocks and at least one accumulation vector processing stage comprised of a plurality of accumulator blocks;
each multiplier block among the plurality of multiplier blocks configured to:
receive a first vector data input sample set and a second vector data input sample set from the plurality of vector data input sample sets from a first input data path and a second input data path among the plurality of input data paths;
multiply the first vector data input sample set to the second vector data input sample set to provide a vector multiply output sample set in a multiply output data path among a plurality of multiply output data paths based on a programmable multiply data path configuration for the multiplier block according to a vector instruction executed by the at least one first vector processing stage; and

each accumulator block among the plurality of accumulator blocks configured to:
receive a first multiply output sample set and a second multiply output sample set from a first multiply output data path and a second multiply output data path, respectively, among a plurality of multiply output data paths;
accumulate the first multiply output sample set with the second multiply output sample set to provide a vector accumulated result sample set based on a programmable data path configuration for the accumulator block according to a vector instruction executed by the at least one second vector processing stage; and
provide the vector accumulated result sample set in the output data path among the plurality of multiple output data paths.

12. The VPE of claim 1 , wherein the at least one vector processing block is not configured to store the least one vector result output sample set in a vector register.

13. The VPE of claim 1 , wherein each vector processing block is further configured to process different bit widths of the plurality of vector data input sample sets based on the programmable data path configuration for the ve

Assignees

• Qualcomm Inc

Inventors

• Khan Raheel

Classifications

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/3897

  with adaptable data path · CPC title

• G06F15/8053

  Vector processors · CPC title

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title