Memory devices and methods of forming the same

Patent metadata

Field	Value
Publication number	US-11978510-B2
Application number	US-202117387964-A
Country	US
Kind code	B2
Filing date	Jul 28, 2021
Priority date	Mar 16, 2020
Publication date	May 7, 2024
Grant date	May 7, 2024

Abstract

The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure including a switching element arranged between a pair of conductors, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure includes a switching element arranged between a pair of conductors, in which the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.

First claim

What is claimed is:

1. A memory device comprising:
a main cell structure including a switching element arranged between a pair of conductors, the switching element is structured as a single dielectric layer; and
a reference cell structure electrically coupled to the main cell structure, the reference cell structure including a switching element arranged between a pair of conductors, the switching element is structured as a single dielectric layer, wherein the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.

2. The device of claim 1 , wherein the switching element of the reference cell structure has a smaller thickness dimension than the switching element of the main cell structure.

3. The device of claim 2 , wherein the thickness dimension of the switching element of the reference cell structure is smaller than the thickness dimension of the switching element of the main cell structure by a factor of 1.5 to 2.

4. The device of claim 2 , wherein the reference cell structure has a reduced intrinsic resistance relative to the main cell structure.

5. The device of claim 1 , wherein the switching element of the reference cell structure has a larger width dimension than the switching element of the main cell structure.

6. The device of claim 1 , wherein the switching element is configured to have a switchable resistance in response to a change in voltage between the pair of conductors.

7. The device of claim 1 , further comprising a main array having a plurality of the main cell structures, each of the main cell structure being electrically coupled to the reference cell structure.

8. The device of claim 1 , wherein the switching element is arranged between a bottom conductor and a top conductor, and further comprising a capping layer disposed on the top conductor.

9. The device of claim 1 , wherein the main cell structure is electrically coupled to the reference cell structure by a sensing amplifier.

10. The device of claim 9 , wherein the main cell structure is configured to generate a read current and the reference cell structure is configured to generate a reference current for comparison with the generated read current.

11. The device of claim 10 , wherein the sensing amplifier is configured to compare the read current generated from the main cell structure with the reference current generated from the reference cell structure.

12. The device of claim 11 , wherein the main cell structure is connected to a planar field-effect transistor.

13. A memory device comprising:
a main cell structure including a switching element arranged between a pair of conductors, the switching element includes a first switching element layer and a second switching element layer, wherein the second switching element layer has a dielectric material different from that of the first switching element layer; and
a reference cell structure electrically coupled to the main cell structure, the reference cell structure including a switching element arranged between a pair of conductors, the switching element includes a third switching element layer, wherein the third switching element layer has the same dielectric material as the first switching element layer, wherein the switching element of the reference cell structure has a dimension that is different from a dimension of the switching element of the main cell structure.

14. The device of claim 13 , wherein the switching element of the reference cell structure has a smaller thickness dimension than the switching element of the main cell structure.

15. The device of claim 14 , wherein the thickness dimension of the switching element of the reference cell structure is smaller than the thickness dimension of the switching element of the main cell structure by a factor of 1.5 to 2.

16. The device of claim 13 , wherein the switching element of the reference cell structure has a larger width dimension than the switching element of the main cell structure.

17. The device of claim 1 , wherein the switching element of the main cell structure has the same dielectric material as the switching element of the reference cell structure.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Hsieh Curtis Chun-I
• Hsu Wei-Hui
• Yi Wanbing
• Jiang Yi
• Kang Kai
• Tan Juan Boon

Classifications

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• H10B63/30

  comprising selection components having three or more electrodes, e.g. transistors · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title

• G11C2013/0045

  Read using current through the cell · CPC title

• G11C2013/0054

  Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell · CPC title