Mcm package isolation through leadframe design and package saw process
US-2020185234-A1 · Jun 11, 2020 · US
Signal isolator having enhanced creepage characteristics
US11973008B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11973008-B2 |
| Application number | US-202217650874-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 14, 2022 |
| Priority date | Sep 18, 2019 |
| Publication date | Apr 30, 2024 |
| Grant date | Apr 30, 2024 |
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Abstract
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Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
First claim
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What is claimed is: 1. A leadless signal isolator IC package, comprising: a leadframe including a die paddle having first and second surfaces, wherein the first and second surfaces are on opposite sides of the die paddle and are parallel to each other, the first surface to support a die and the second surface being exposed on an exterior surface of the IC package; and a die supported by the die paddle, the die having a width, wherein a width of the second surface of the die paddle is less than the width of the die along an entire length of the die and edges of the die along the length of the die are outside of edges of the exposed second surface of the die paddle, and wherein a width of the first surface of the die paddle is greater than the width of the die along the entire length of the die. 2. The signal isolator IC package according to claim 1 , wherein the die includes pads located within the width of the second surface of the die paddle. 3. The signal isolator IC package according to claim 1 , wherein the die includes first and second voltage domains. 4. The signal isolator package according to claim 1 , wherein the die paddle comprises a middle portion having a first thickness and outer portions having a second thickness that is less than the first thickness. 5. The signal isolator package according to claim 1 , wherein the die includes pads located within the width of the second surface of the die paddle, and further including at least one wirebond connected to at least one of the pads. 6. A method for providing a leadless signal isolator IC package, comprising: employing a leadframe including a die paddle having first and second surfaces, wherein the first and second surfaces are on opposite sides of the die paddle and are parallel to each other the first surface to support a die and the second surface being exposed on an exterior surface of the IC package; and employing a die supported by the die paddle, the die having a width, wherein a width of the second surface of the die paddle is less than the width of the die along an entire length of the die and edges of the die along the length of the die are outside of edges of the exposed second surface of the die paddle, and wherein a width of the first surface of the die paddle is greater than the width of the die along the entire length of the die. 7. The method according to claim 6 , wherein the die includes pads located within the width of the second surface of the die paddle. 8. The method according to claim 6 , wherein the die includes first and second voltage domains. 9. The method according to claim 6 , wherein the die paddle comprises a middle portion having a first thickness and outer portions having a second thickness that is less than the first thickness. 10. The method according to claim 6 , wherein the die includes pads located within the width of the second surface of the die paddle, and further including at least one wirebond connected to at least one of the pads.
Assignees
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Classifications
between a chip and a laterally-adjacent insulating package substrate, interpose or RDL · CPC title
Top-view layouts, e.g. mirror arrays · CPC title
Bond pads specially adapted therefor · CPC title
Multiple chips on leadframes · CPC title
Materials of bond wires · CPC title
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- What does patent US11973008B2 cover?
- Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.
- Who is the assignee on this patent?
- Allegro Microsystems Llc
- What technology area does this patent fall under?
- Primary CPC classification H10W70/411. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Apr 30 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).