Gate stacks with multiple high-κ dielectric layers

Patent metadata

Field	Value
Publication number	US-11961895-B2
Application number	US-202117447109-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Sep 8, 2021
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A first semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a second high-κ dielectric layer over the first high-κ dielectric layer, a Ti—Si mixing layer over the second high-κ dielectric layer, and a gate electrode layer over the Ti—Si mixing layer. A second semiconductor device includes an interfacial layer over a substrate, a first high-κ dielectric layer over the interfacial layer, a Ti—Si mixing layer over the first high-κ dielectric layer, a second high-κ dielectric layer over the Ti—Si mixing layer, and a gate electrode layer over the second high-κ dielectric layer. The method includes forming an interfacial layer over a substrate, forming a first high-κ dielectric layer over the interfacial layer, forming a second high-κ dielectric layer over the first high-κ dielectric layer, and forming a gate electrode layer over the second high-κ dielectric layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
an interfacial layer over a substrate;
a first high-k dielectric layer over the interfacial layer;
a Ti-dopant mixing layer over the first high-k dielectric layer;
a second high-k dielectric layer over the Ti-dopant mixing layer;
a Ti—Si mixing layer over the second high-k dielectric layer; and
a gate electrode layer over the Ti—Si mixing layer.

2. The semiconductor device of claim 1 , further comprising a dipole at an interface between the first high-k dielectric layer and the interfacial layer.

3. The semiconductor device of claim 1 , wherein the Ti-dopant mixing layer comprises lanthanum.

4. The semiconductor device of claim 1 , wherein the gate electrode layer is an electrode selected from the group consisting of TiN, polysilicon, aluminum, tungsten, a silicide, ruthenium(IV) oxide, WN/RuO 2 , tantalum, TiAlC, TiAl, Ti, niobium, and tantalum nitride.

5. The semiconductor device of claim 1 , wherein the first high-k dielectric layer and the second high-k dielectric layer are independently selected from the group consisting of hafnium oxide, zirconium oxide, tantalum oxide, strontium titanate, titanium oxide, aluminum oxide, and yttrium oxide.

6. The semiconductor device of claim 1 , wherein the first high-k dielectric layer is thicker than the second high-k dielectric layer.

7. The semiconductor device of claim 1 , wherein the Ti-dopant mixing layer comprises a dopant selected from the group consisting of lanthanum, zirconium, magnesium, aluminum, and yttrium.

8. The semiconductor device of claim 1 , wherein at least one of the first high-k dielectric layer and the second high-k dielectric layer is an oxide of hafnium.

9. The semiconductor device of claim 1 , wherein the first high-k dielectric layer and the second high-k dielectric layer each have a dielectric constant above approximately 12.

10. The semiconductor device of claim 1 , wherein the first high-k dielectric layer has a thickness of about 10 Å-30 Å, and the second high-k dielectric layer has a thickness of about 1 Å-6 Å.

11. A method of forming a semiconductor device stack, comprising:
forming an interfacial layer on a substrate;
forming a first high-k dielectric layer over the interfacial layer;
forming a Ti-dopant mixing layer directly over the first high-k dielectric layer;
forming a second high-k dielectric layer over the over the Ti-dopant mixing layer; and
forming a gate electrode layer over the second high-k dielectric layer.

12. The method of claim 11 , further comprising forming a Ti—Si mixing layer directly over the second high-k dielectric layer.

13. The method of claim 11 , further comprising:
depositing a high-k dielectric material on the Ti-dopant mixing layer to form the second high-k dielectric layer;
inducing a dipole at an interface between the interfacial layer and the first high-k dielectric layer; and
forming a Ti—Si mixing layer directly over the second high-k dielectric layer.

14. The method of claim 11 , further comprising:
inducing a dipole at an interface between the interfacial layer and the first high-k dielectric layer;
removing the Ti-dopant mixing layer;
forming a Ti—Si mixing layer over the first high-k dielectric layer; and
depositing a high-k dielectric material on the Ti—Si mixing layer to form the second high-k dielectric layer.

15. The method of claim 11 , wherein the Ti-dopant mixing layer comprises a dopant selected from the group consisting of lanthanum, magnesium, aluminum, and yttrium.

16. The method of claim 11 , further comprising forming a second gate electrode layer over the gate electrode layer.

17. The method of claim 11 , wherein the forming the Ti-dopant mixing layer comprises:
forming a blocking layer over a dipole-inducing dopant material;
patterning the blocking layer; and
thinning the patterned blocking layer.

18. The method of claim 11 , wherein the gate electrode layer is selected from the group consisting of TiN, polysilicon, aluminum, tungsten, TiAlC, TiAl, Ti, a silicide, ruthenium(IV) oxide, WN/RuO2, tantalum, niobium, and tantalum nitride.

19. The method of claim 11 , further comprising, before forming the gate electrode layer, inducing a dipole between the interfacial layer and the first high-k dielectric layer.

20. The method of claim 19 , wherein the inducing comprises forming an annealing stack comprising a film of TiN on the Ti-dopant mixing layer.

Assignees

• IBM

Inventors

• Bao Ruqiang
• Ramachandran Ravikumar
• Linder Barry
• Siddiqui Shahab
• Mataev Elnatan

Classifications

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D64/685 Primary

  being perpendicular to the channel plane · CPC title

• H10D64/01

  Manufacture or treatment · CPC title