Gate stack formed with interrupted deposition processes and laser annealing

US9613870B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9613870-B2
Application numberUS-201514755829-A
CountryUS
Kind codeB2
Filing dateJun 30, 2015
Priority dateJun 30, 2015
Publication dateApr 4, 2017
Grant dateApr 4, 2017

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.

First claim

Opening claim text (preview).

What is claimed: 1. A structure, comprising: a high-k gate dielectric stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous; a blocking layer deposited on a pFET side of the high-k dielectric stack; and a lanthanum oxide film deposited on the blocking material and an exposed portion of the high-k bilayer or nanolaminate on a nFET side of the high-k dielectric stack. 2. The structure of claim 1 , wherein crystallites of the crystallized high-k bilayer is below 2 nm. 3. The structure of claim 2 , wherein a thickness of the crystallized portion of the high-k bilayer is less than 12 Å. 4. The structure of claim 3 , wherein the high-k bilayer contains La or Mg atoms. 5. The structure of claim 4 , wherein an amount of atoms of the La or Mg atoms is larger than 1.5e14 atoms/cm 2 . 6. The structure of claim 4 , further comprising multiple nFET transistors where at least one of the nFET transistors has the La or Mg atoms. 7. The structure of claim 6 , wherein the at least one of the nFET transistors with the La or Mg atoms have threshold voltages separated by at least 100 mV. 8. The structure of claim 6 , wherein the nFET transistors with the La or Mg atoms have threshold voltages separated by at least 100 mV. 9. The structure of claim 6 , wherein the La or Mg atoms will form dipoles by binding with oxygen. 10. The structure of claim 1 , further comprising multiple nFET transistors with the high-k dielectric gate stack with the high-k bilayer. 11. The structure of claim 10 , wherein the multiple nFET transistors with the high-k dielectric gate stack with the high-k bilayer comprise La or Mg doping. 12. The structure of claim 1 , wherein the blocking material comprises at least TiN or a or a composite sandwich of TiN/oxide/TiN. 13. The structure of claim 12 , wherein a thickness of the blocking material is less than 50 Å. 14. The structure of claim 1 , further comprising a capping layer formed over the lanthanum oxide film on the nFET transistor side. 15. The structure of claim 14 , further comprising an a-Si capping layer deposited on the capping layer. 16. The structure of claim 15 , wherein a thickness of the a-Si capping layer is less than 20 Å. 17. The structure of claim 1 , further comprising multiple nFET transistors with the high-k dielectric gate stack with the high-k bilayer. 18. The structure of claim 17 , wherein the multiple nFET transistors with the high-k dielectric gate stack with the high-k bilayer comprise La or Mg doping. 19. The structure of claim 18 , wherein the multiple nFET transistors with the high-k dielectric gate stack with the high-k bilayer comprise La or Mg doping of different levels. 20. A structure, comprising: a high-k gate dielectric stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous; and multiple nFET transistors with the high-k dielectric gate stack with the high-k bilayer, wherein the multiple nFET transistors with the high-k dielectric gate stack with the high-k bilayer comprise La or Mg doping of different levels.

Assignees

Inventors

Classifications

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20) · CPC title

  • the material containing zirconium, e.g. ZrO2 · CPC title

  • the material containing hafnium, e.g. HfO2 · CPC title

  • to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

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Frequently asked questions

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What does patent US9613870B2 cover?
Semiconductor structures and methods of fabricating the same using interrupted deposition processes and multiple laser anneals are provided. The structure includes a high-k gate stack with a high-k bilayer or nanolaminate where a bottom portion of the bilayer is crystallized while a top portion of the bilayer is amorphous.
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H01L21/823462. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 04 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).