Inversion thickness reduction in high-k gate stacks formed by replacement gate processes

Patent metadata

Field	Value
Publication number	US-9252229-B2
Application number	US-201213605267-A
Country	US
Kind code	B2
Filing date	Sep 6, 2012
Priority date	May 4, 2011
Publication date	Feb 2, 2016
Grant date	Feb 2, 2016

Abstract

A method of forming a transistor device includes forming an interfacial layer on a semiconductor substrate, corresponding to a region between formed doped source and drain regions in the substrate; forming a high dielectric constant (high-k) layer on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5; forming a doped metal layer on the high-k layer; performing a thermal process so as to cause the doped metal layer to scavenge oxygen atoms diffused from the interfacial layer such that a final thickness of the interfacial layer is less than about 5 angstroms (Å); and forming a metal gate material over the high-k dielectric layer.

First claim

What is claimed is:

1. A transistor device, comprising:
an interfacial layer formed on a semiconductor substrate, corresponding to a region between doped source and drain regions in the substrate, the interfacial layer having a thickness less than about 5 angstroms (Å);
a high dielectric constant (high-k) layer formed on the interfacial layer, the high-k layer having a dielectric constant greater than about 7.5, the high-k layer having vertical sidewalls abutting vertical sidewalls of gate sidewall spacers;
a metal gate material formed over the high-k dielectric layer; and
a doped metal layer formed between the high-k layer and the metal gate material, the doped metal layer having vertical sidewalls abutting the vertical sidewalls of the high-k layer, wherein the doped metal layer further comprises first and second metallic compound layers that surround a scavenging metal layer, with a material of the first and second metallic compound layers including one of a conductive transition metal nitride and a conductive transition metal carbide, and the scavenging metal layer comprising a doped metal selected such that a Gibbs free energy change of a chemical reaction, in which an atom constituting a channel combines with a metal oxide material including the doped metal and oxygen to form the doped metal in elemental form and oxide of the atom constituting a channel, is positive.

2. The device of claim 1 , wherein the first and second metallic compound layers are selected from the group of TiN, TiC, TaN, TaC, and combinations thereof.

3. The device of claim 2 , wherein the doped metal is selected from the group of Al, Be, Mg, Ca, Sr, Ba, Sc, Y, La, Ti, Zr, Hf, Dy, Lu, Er, Pr, and Ce, and combinations thereof.

4. The device of claim 3 , wherein the metal gate material is selected from the group of Al, Ta, TaN, W, WN, Ti and TiN.

5. The device of claim 4 , wherein the interfacial layer, the high-k layer, and the doped metal layer are formed between preformed gate sidewall spacers in accordance with a replacement gate scheme.

Assignees

• Ando Takashi
• Narayanan Vijay
• IBM

Inventors

• Ando Takashi
• Narayanan Vijay

Classifications

• H10D64/01338

  with a treatment, e.g. annealing, after the formation of the conductor · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title

• H10D30/601

  having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  (lightly doped source or drain extensions for TFTs H10D30/6715) · CPC title

• H10D30/0273

  forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology · CPC title

• H10D64/667 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title