Transistor devices with high-k insulation layers

Patent metadata

Field	Value
Publication number	US-9425194-B2
Application number	US-201514819646-A
Country	US
Kind code	B2
Filing date	Aug 6, 2015
Priority date	Jul 30, 2012
Publication date	Aug 23, 2016
Grant date	Aug 23, 2016

Abstract

An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

First claim

What is claimed:

1. An integrated circuit product, comprising:
a first transistor positioned in and above a first active region of a semiconducting substrate, wherein said first transistor comprises a first gate material stack and has a first gate length, said first gate material stack comprising a first gate dielectric layer having a first thickness positioned above said first active region and at least one layer of metal positioned above said first gate dielectric layer, wherein said first gate dielectric layer comprises a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on said layer of said first high-k insulating material; and
a second transistor positioned in and above a second active region of said semiconducting substrate, wherein said second transistor comprises a second gate material stack and has a second gate length, said second gate material stack comprising a second gate dielectric layer having a second thickness positioned above said second active region and at least one layer of metal positioned above said second gate dielectric layer, wherein said second gate dielectric layer comprises a layer of said second high-k insulating material, said second gate length being less than said first gate length and said second thickness being less than said first thickness.

2. The integrated circuit product of claim 1 , wherein said first high-k insulating material and said second high-k insulating material comprise a same high-k insulating material.

3. The integrated circuit product of claim 1 , wherein said first high-k insulating material and said second high-k insulating material comprise different high-k insulating materials.

4. The integrated circuit product of claim 1 , wherein a thickness of said layer of said first high-k insulating material is substantially the same as a thickness of said layer of said second high-k insulating material.

5. The integrated circuit product of claim 1 , wherein a thickness of said layer of said first high-k insulating material is different from a thickness of said layer of said second high-k insulating material.

6. The integrated circuit product of claim 1 , wherein said first gate dielectric layer further comprises a layer of an interfacial dielectric material positioned between said first active region and said layer of said first high-k insulating material and said second gate dielectric layer further comprises a layer of said interfacial dielectric material positioned between said second active region and said layer of said second high-k insulating material.

7. The integrated circuit product of claim 6 , wherein said layers of said interfacial dielectric material comprise one of silicon oxide and silicon oxynitride.

8. The integrated circuit product of claim 1 , wherein said first transistor comprises an input/output circuit of said integrated circuit product and said second transistor comprises a logic circuit of said integrated circuit product.

9. An integrated circuit product, comprising:
a first transistor having a first gate length positioned in and above a first active region of a semiconducting substrate and comprising a first gate structure, said first gate structure comprising a first gate dielectric layer having a first thickness positioned above said first active region and a first work function material layer positioned above said first gate dielectric layer, wherein said first gate dielectric layer comprises a first layer of a first high-k insulating material and a second layer of said first high-k insulating material positioned on said first layer of said first high-k insulating material; and
a second transistor having a second gate length that is less than said first gate length positioned in and above a second active region of said semiconducting substrate and comprising a second gate structure, said second gate structure comprising a second gate dielectric layer having a second thickness that is less than said first thickness positioned above said second active region and a second work function material layer positioned above said second gate dielectric layer, wherein said second gate dielectric layer comprises a third layer of said first high-k insulating material.

10. The integrated circuit product of claim 9 , wherein each of said first, second, and third layers of said high-k insulating material has the same thickness.

11. The integrated circuit product of claim 10 , wherein said first thickness of said first gate dielectric layer is approximately two times said second thickness of said second gate dielectric layer.

12. The integrated circuit product of claim 9 , wherein a thickness of said first layer of said high-k insulating material is the same as a thickness of said third layer of said high-k insulating material and different from a thickness of said second layer of said high-k insulating material.

13. The integrated circuit product of claim 9 , wherein said first gate dielectric layer comprises a first layer of interfacial dielectric material positioned between said first active region and said first layer of said high-k insulating material and said second gate dielectric layer comprises a second layer of said interfacial dielectric material positioned between said second active region and said third layer of said high-k insulating material, said first and second layers of said interfacial dielectric material comprising one of silicon oxide and silicon oxynitride.

14. The integrated circuit product of claim 9 , wherein said first transistor comprises an input/output circuit of said integrated circuit product and said second transistor comprises a logic circuit of said integrated circuit product.

15. An integrated circuit product, comprising:
a first transistor positioned in and above a first active region of a semiconducting substrate, wherein said first transistor comprises a first gate structure and has a first gate length, said first gate structure comprising:
a first interfacial dielectric layer positioned on said first active region;
a first layer of high-k insulating material positioned on said first interfacial dielectric layer;
a second layer of high-k insulating material positioned on said first layer of high-k insulating material;
a first work function material layer positioned above said second layer of high-k insulating material; and
a first conductive material layer positioned above said first work function material layer; and

a second transistor positioned in and above a second active region of a semiconducting substrate, wherein said second transistor comprises a second gate structure and has a second gate length that is less than said first gate length, said second gate structure comprising:
a second interfacial dielectric layer positioned on said second active region;
a third layer of high-k insulating material positioned on said second interfacial dielectric layer;
a second work function material layer positioned above said third layer of high-k insulating material; and
a second conductive material layer positioned above said second work function material layer.

16. The integrated circuit product of claim 15 , wherein said first, second, and third layers of high-k insulating material comprise a same high-k insulating material.

17. The integrated circuit product of claim 15 , wherein said first and third layers of high-k insulating material are comprised of a same high-k insulating material and said second layer of high-k insulating material is comprised of a different high-k insulating material from said first and third layers

Assignees

• Globalfoundries Inc

Inventors

• Gerhardt Martin
• Flachowsky Stefan
• Kessler Matthias

Classifications

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10D84/0181

  Manufacturing their gate insulating layers · CPC title

• H10D84/0177

  the gate conductors having different materials or different implants · CPC title

• H10D84/0144 Primary

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title