Method for forming semiconductor structure and semiconductor structure

Patent metadata

Field	Value
Publication number	US-11961881-B2
Application number	US-202117445993-A
Country	US
Kind code	B2
Filing date	Aug 26, 2021
Priority date	Aug 13, 2020
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A method for forming a semiconductor structure includes providing a semiconductor substrate, which at least includes discrete conducting layers in the semiconductor substrate; forming discretely arranged supporting structures on the semiconductor substrate, capacitor openings being included between the supporting structures; forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the conducting layers; forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and forming an upper electrode covering the capacitor dielectric layer, to form capacitor structures.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a semiconductor substrate, which at least comprises discrete conducting layers in the semiconductor substrate;
forming a bottom conducting layer on the semiconductor substrate, the bottom conducting layer being electrically connected with the conducting layers;
forming discretely arranged supporting structures on the bottom conducting layer, capacitor openings being comprised between the supporting structures;
forming lower electrodes on sidewalls of the supporting structures, the lower electrodes being electrically connected with the bottom conducting layer;
etching away the bottom conducting layer exposed from the bottom of the capacitance openings, the bottom conducting layer located only between the semiconductor substrate and the supporting structure;
forming a capacitor dielectric layer covering tops of the supporting structures, sidewalls of the lower electrodes, and bottoms of the capacitor openings; and
forming an upper electrode covering the capacitor dielectric layer, to form capacitor structures.

2. The method for forming a semiconductor structure of claim 1 , wherein said forming the discretely arranged supporting structures on the semiconductor substrate comprises:
forming a supporting layer on the semiconductor substrate; and
patterning the supporting layer to form the capacitor openings, the remaining supporting layer forming the supporting structures.

3. The method for forming a semiconductor structure of claim 2 , wherein the capacitor openings at least expose a part of a top surface of each discrete conducting layer.

4. The method for forming a semiconductor structure of claim 1 , wherein each of the supporting structures is a stacked structure formed by sequential stacking.

5. The method for forming a semiconductor structure of claim 4 , wherein the stacked structure comprises a bottom supporting layer and a filling layer that are formed by sequentially stacking.

6. The method for forming a semiconductor structure of claim 2 , wherein said patterning the supporting layer to form a plurality of discrete capacitor openings comprises:
sequentially forming a mask layer and a patterned photoresist layer on the supporting layer;
patterning the mask layer based on the photoresist layer; and
etching the supporting layer based on the patterned mask layer to form the capacitor openings.

7. The method for forming a semiconductor structure of claim 1 , wherein said forming the lower electrodes electrically connected with the bottom conducting layer on the sidewalls of the supporting structures comprises:
forming a top conducting layer on the tops and sidewalls of the supporting structures and the bottoms of the capacitor openings; and
removing the top conducting layer on the tops of the supporting structure and the bottoms of the capacitor openings to form the lower electrodes on the sidewalls of the supporting structures.

8. The method for forming a semiconductor structure of claim 7 , wherein a process for removing the top conducting layer on the tops of the supporting structures comprises chemical mechanical polishing.

9. The method for forming a semiconductor structure of claim 1 , wherein said forming the upper electrode covering the capacitor dielectric layer comprises:
forming a first conducting layer covering the capacitor dielectric layer; and
forming a second conducting layer filling gaps between the first conducting layer, a top surface of the second conducting layer being parallel to a top surface of the first conducting layer on the supporting structure, and a height of the top surface of the second conducting layer being greater than a height of the top surface of the first conducting layer on the supporting structure.

10. The method for forming a semiconductor structure of claim 9 , wherein said forming the second conducting layer filling the gaps between the first conducting layer comprises:
forming a second conducting film filling the gaps between the first conducting layer, a height of a top surface of the second conducting film being greater than a height of the top surface of the first conducting layer on the supporting structure; and
performing chemical mechanical polishing on the top surface of the second conducting film to form the second conducting layer.

11. A semiconductor structure, comprising:
a semiconductor substrate, wherein at least discrete conducting layers are comprised in the semiconductor substrate;
multiple discrete supporting structures, located on the semiconductor substrate; and
capacitor structures supported by the supporting structures, wherein each capacitor structure comprises:
a lower electrode, located on a sidewall of a corresponding one of the supporting structures;
a bottom conducting layer, located only between the semiconductor substrate and the supporting structure and configured to electrically connect the lower electrode and the conducting layer; wherein the supporting structure is on the bottom conducting layer;
a capacitor dielectric layer, located at a top of the supporting structure, a sidewall of the lower electrode, and a bottom of a gap between the supporting structures; and
an upper electrode, located on the capacitor dielectric layer.

12. The semiconductor structure of claim 11 , wherein gaps between the supporting structures at least expose a part of a top surface of each discrete conducting layer; and the lower electrode is configured to connect to the exposed top surface of the discrete conducting layer.

13. The semiconductor structure of claim 11 , wherein the upper electrode comprises:
a first conducting layer, located on the capacitor dielectric layer; and
a second conducting layer, filling gaps between the first conducting layer, a height of a top surface of the second conducting layer being greater than a height of a top surface of the first conducting layer on the supporting structure.

Assignees

• Changxin Memory Tech Inc

Inventors

• Wang Lingxiang

Classifications

• H10D1/043

  using patterning processes to form electrode extensions, e.g. etching · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H01L28/91 Primary

  Electricity · mapped topic

• H01L28/92

  Electricity · mapped topic