Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry

Patent metadata

Field	Value
Publication number	US-10355002-B2
Application number	US-201715667159-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Aug 31, 2016
Publication date	Jul 16, 2019
Grant date	Jul 16, 2019

Abstract

A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed.

First claim

The invention claimed is:

1. A memory cell comprising:
first and second transistors laterally displaced relative one another; and
a capacitor above the first and second transistors; the capacitor comprising a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node; the capacitor dielectric material extending across a top of the container-shape first capacitor node.

2. The memory cell of claim 1 wherein the first and second transistors are each elevationally-extending.

3. The memory cell of claim 2 wherein the first and second transistors are each vertical or within 10° of vertical.

4. The memory cell of claim 1 wherein the capacitor dielectric material is directly against the top of the container-shape first capacitor node.

5. The memory cell of claim 1 wherein the second capacitor node is directly against a top of the capacitor dielectric material.

6. The memory cell of claim 1 wherein the first capacitor node is directly above the first current node of the first transistor.

7. The memory cell of claim 1 wherein the second capacitor node is directly above the first current node of the second transistor.

8. The memory cell of claim 7 wherein the second capacitor node is directly above the first current node of the first transistor.

9. The memory cell of claim 1 wherein the first capacitor node is directly electrically coupled with the first current node of the first transistor and the second capacitor node is directly electrically coupled with the first current node of the second transistor.

10. The memory cell of claim 1 wherein the first and second transistors are in a common horizontal plane relative one another.

11. The memory cell of claim 1 wherein the container-shape first capacitor node and the first transistor are longitudinally coaxial.

12. A memory cell comprising:
first and second transistors laterally displaced relative one another; and
a capacitor above the first and second transistors; the capacitor comprising a conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first and second capacitor nodes; the second capacitor node being directly against a top of the capacitor dielectric material that is between the first and second capacitor nodes.

13. The memory cell of claim 12 wherein the first capacitor node comprises a container-shape.

14. A two transistor-one capacitor memory cell comprising:
first and second transistors laterally displaced relative one another; and
a capacitor above the first and second transistors; the capacitor comprising a conductive first capacitor node directly above and electrically coupled with a first current node of the first transistor, a conductive second capacitor node directly above the first and second transistors and electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first and second capacitor nodes; the second capacitor node comprising an elevationally-extending conductive pillar directly above the first current node of the second transistor, the conductive pillar having an elevationally outer portion that is of hourglass shape in horizontal cross-section.

15. The memory cell of claim 14 wherein the pillar and the second transistor are longitudinally coaxial.

16. The memory cell of claim 14 wherein laterally-extending end surfaces of the hourglass shape are concave.

17. The memory cell of claim 14 wherein longitudinally-extending side surfaces of the hourglass shape are circularly concave between longitudinal ends of the hourglass shape.

18. The memory cell of claim 14 wherein the memory cell occupies a maximum horizontal area of no more than 5.2F 2 , where “F” is minimum horizontal width of a smaller, if any, of the top of an elevationally outermost surface the first current node of the first and second transistors.

19. The memory cell of claim 18 wherein the maximum horizontal area is less than 5.2F 2 .

Assignees

• Micron Technology Inc

Inventors

• Sills Scott E

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H01L21/76897

  Electricity · mapped topic

• H01L28/91

  Electricity · mapped topic

• H01L28/60

  Electricity · mapped topic

• H01L27/10844 Primary

  Electricity · mapped topic