Memory Cells, Arrays Of Two Transistor-One Capacitor Memory Cells, Methods Of Forming An Array Of Two Transistor-One Capacitor Memory Cells, And Methods Used In Fabricating Integrated Circuitry

Patent metadata

Field	Value
Publication number	US-2018197864-A1
Application number	US-201715852870-A
Country	US
Kind code	A1
Filing date	Dec 22, 2017
Priority date	Jan 12, 2017
Publication date	Jul 12, 2018
Grant date	—

Abstract

A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a conductive first capacitor node directly above and electrically coupled to a first node of the first transistor. A conductive second capacitor node is directly above the first and second transistors and is electrically coupled to a first node of the second transistor. A capacitor insulator is between the first and second capacitor nodes. The second capacitor node comprises an elevationally-extending conductive pillar directly above the first node of the second transistor. The conductive pillar has an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section. Other memory cells, including arrays of memory cells are disclosed as are methods.

First claim

1 . A memory cell comprising:
first and second transistors laterally displaced relative one another and comprising a longitudinally-elongated access line that is common to the first and second transistors; and
a capacitor above the first and second transistors; the capacitor comprising:
a conductive first capacitor node electrically coupled to a first node of the first transistor;
a conductive second capacitor node electrically coupled to a first node of the second transistor;
a capacitor insulator between the first and second capacitor nodes; and
the second capacitor node comprising:
a first elevationally-extending conductive pillar above the first node of the first transistor;
a second elevationally-extending conductive pillar above the first node of the second transistor; and
conductive material atop, extending between, and directly electrically coupling together the first and second pillars; the conductive material being longitudinally elongated at an angle relative to longitudinal orientation of the longitudinally-elongated access line within the memory cell.

2 . The memory cell of claim 1 wherein the angle is at least 25° from the longitudinal orientation of the longitudinally-elongated access line within the memory cell.

3 . The memory cell of claim 2 wherein the angle is 25° to 60°.

4 . The memory cell of claim 3 wherein the angle is more than 45°.

5 . The memory cell of claim 3 wherein the angle is less than 45°.

6 . The memory cell of claim 3 wherein the angle is 45°.

7 . The memory cell of claim 1 wherein the first and second transistors are each elevationally-extending.

8 . The memory cell of claim 1 wherein the second capacitor node is directly against a top of the capacitor insulator.

9 . The memory cell of claim 1 wherein the first capacitor node is directly above the first node of the first transistor.

10 . The memory cell of claim 1 wherein the second capacitor node is directly above the first node of the second transistor.

11 . The memory cell of claim 10 wherein the second capacitor node is directly above the first node of the first transistor.

12 . The memory cell of claim 1 wherein the first capacitor node is directly electrically coupled to the first node of the first transistor and the second capacitor node is directly electrically coupled to the first node of the second transistor.

13 . The memory cell of claim 1 wherein the first and second transistors are in a common horizontal plane relative one another.

14 . The memory cell of claim 1 wherein the first capacitor node and the first transistor are longitudinally coaxial.

15 . The memory cell of claim 1 wherein the second pillar has an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section.

16 . A memory cell comprising:
first and second transistors laterally displaced relative one another; a capacitor above the first and second transistors; the capacitor comprising:
a conductive first capacitor node electrically coupled to a first node of the first transistor;
a conductive second capacitor node electrically coupled to a first node of the second transistor;
a capacitor insulator between the first and second capacitor nodes; and
the second capacitor node comprising:
a first elevationally-extending conductive pillar above the first node of the first transistor;
a second elevationally-extending conductive pillar above the first node of the second transistor; and
conductive material atop, extending between, and directly electrically coupling together the first and second pillars; and

a first digit line electrically coupled to a second node of the first transistor and a second digit line electrically coupled to a second node of the second transistor, the first and second digit lines being longitudinally elongated, the conductive material of the second capacitor node being longitudinally elongated at an angle other than 90° relative to longitudinal orientation of each of the first and second longitudinally-elongated digit lines.

17 - 26 . (canceled)

27 . A memory cell comprising:
first and second transistors laterally displaced relative one another and comprising an access line that is common to the first and second transistors; a capacitor above the first and second transistors; the capacitor comprising a conductive first capacitor node electrically coupled to a first node of the first transistor, a conductive second capacitor node electrically coupled to a first node of the second transistor, and a capacitor insulator between the first and second capacitor nodes; and a second node of the first transistor being electrically coupled to a first digit line at a first longitudinal location along the first digit line and a second node of the second transistor being electrically coupled to a second digit line at a second longitudinal location along the second digit line, the first and second digit lines being parallel relative one another within the memory cell, a horizontal line through centers of the first and second longitudinal locations being angled at least 30° relative to longitudinal orientation of the first and second digit lines within the memory cell.

28 - 34 . (canceled)

35 . A two transistor-one capacitor memory cell comprising:
first and second transistors laterally displaced relative one another; and a capacitor above the first and second transistors; the capacitor comprising a conductive first capacitor node directly above and electrically coupled to a first node of the first transistor, a conductive second capacitor node directly above the first and second transistors and electrically coupled to a first node of the second transistor, and a capacitor insulator between the first and second capacitor nodes; the second capacitor node comprising an elevationally-extending conductive pillar directly above the first node of the second transistor, the conductive pillar having an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section.

36 - 37 . (canceled)

38 . An array of two transistor-one capacitor memory cells comprising:
columns of digit lines and rows of access lines, the digit lines comprising first alternating digit lines and second alternating digit lines, the second alternating digit lines individually being between immediately adjacent of the first alternating digit lines; rows of elevationally-extending first field effect transistors individually having an elevationally inner of their source/drain regions electrically coupled to one of the individual first alternating digit lines, rows of elevationally-extending second first field effect transistors individually having an elevationally inner of their source/drain regions electrically coupled to one of the individual second alternating digit lines, channels of the first and second transistors being inter-row staggered, individual of the rows of access lines being operatively adjacent the channels of the first and second transistors; and individual capacitors above individual pairs of one of the first transistors and one of the second transistors; the capacitors individually comprising a conductive first capacitor node electrically coupled to the first transistor of the individual pair, a conductive second capacitor node electrically coupled to the second transistor of the individual pair, and a capacitor insulator between the first and second capacitor nodes.

39 - 44 . (canceled)

Assignees

• Micron Technology Inc

Inventors

• Sills Scott E

Classifications

• H01L27/10802 Primary

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title