Memory Cells, Methods Of Forming An Array Of Two Transistor-One Capacitor Memory Cells, And Methods Used In Fabricating Integrated Circuitry

Patent metadata

Field	Value
Publication number	US-2020219886-A1
Application number	US-202016821746-A
Country	US
Kind code	A1
Filing date	Mar 17, 2020
Priority date	Aug 31, 2016
Publication date	Jul 9, 2020
Grant date	—

Abstract

A memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a container-shape conductive first capacitor node electrically coupled with a first current node of the first transistor, a conductive second capacitor node electrically coupled with a first current node of the second transistor, and a capacitor dielectric material between the first capacitor node and the second capacitor node. The capacitor dielectric material extends across a top of the container-shape first capacitor node. Additional embodiments and aspects, including method, are disclosed.

First claim

1 - 34 . (canceled)

35 . A method of forming a memory cell, the method comprising:
etching a container opening through at least upper and lower masking materials to a location of a first transistor of the memory cell; forming a container-shape electrode comprising bottom electrode material in the container opening; forming insulator material over the bottom electrode material in the container opening; forming top electrode material over the insulator material in the container opening; removing the upper masking material to expose a portion of the insulator material above the lower masking material; forming a spacer around the exposed portion of the insulator material; using at least the spacer as an etch mask while etching a contact opening to a location of a second transistor of the memory cell; and forming conductive material in the contact opening.

36 . The method of claim 35 wherein the upper and lower masking materials are of different compositions relative one another.

37 . The method of claim 35 wherein the upper masking material comprises carbon.

38 . The method of claim 35 wherein the lower masking material comprises silicon nitride.

39 . The method of claim 35 wherein the upper masking material comprises carbon and the lower masking material comprises silicon nitride.

40 . The method of claim 35 comprising removing all remaining of the lower masking material.

41 . The method of claim 40 wherein the removing all the remaining of the lower masking material occurs after forming the conductive material.

42 . The method of claim 35 comprising removing all remaining of the spacer.

43 . The method of claim 42 wherein the removing all the remaining of the spacer occurs after forming the conductive material.

44 . The method of claim 35 comprising removing all remaining of the lower masking material and removing all remaining of the spacer.

45 . The method of claim 44 wherein the removing all the remaining of the spacer and the removing all the remaining lower masking material occur after forming the conductive material.

46 . A method of forming a memory cell, the method comprising:
etching a container opening through at least upper and lower masking materials to a location of a first transistor of the memory cell; forming a container-shape electrode comprising bottom electrode material in the container opening; forming insulator material over the bottom electrode material in the container opening; forming top electrode material over the insulator material in the container opening; removing the upper masking material to cause the top electrode material to project upwardly from an exposed uppermost surface of the lower masking material; forming a spacer around the upwardly projecting top electrode material; using at least the spacer as an etch mask while etching a contact opening to a location of a second transistor of the memory cell; and forming conductive material in the contact opening.

47 . The method of claim 46 wherein the upper and lower masking materials are of different compositions relative one another.

48 . The method of claim 46 wherein the upper masking material comprises carbon.

49 . The method of claim 46 wherein the lower masking material comprises silicon nitride.

50 . The method of claim 46 wherein the upper masking material comprises carbon and the lower masking material comprises silicon nitride.

51 . A method of forming a memory cell, the method comprising:
etching a container opening through masking material to a location of a first transistor of the memory cell; forming a container-shape electrode comprising bottom electrode material in the container opening; forming insulator material over the bottom electrode material in the container opening; forming top electrode material over the insulator material in the container opening; removing some of the masking material to expose a portion of the insulator material above the masking material; forming a spacer around the exposed portion of the insulator material; using at least the spacer as an etch mask while etching a contact opening to a location of a second transistor of the memory cell; and forming conductive material in the contact opening.

52 . The method of claim 51 comprising removing all remaining of the spacer.

53 . The method of claim 52 wherein the removing all the remaining of the spacer occurs after forming the conductive material.

54 . A method of forming a memory cell, the method comprising:
etching a first opening through masking material to a location of a first transistor of the memory cell; forming bottom electrode material in the first opening; forming insulator material over the bottom electrode material in the first opening; forming top electrode material over the insulator material in the first opening; removing some of the masking material to cause the top electrode material to project upwardly; forming a spacer around the upwardly projecting top electrode material; using at least the spacer as an etch mask while etching a second opening to a location of a second transistor of the memory cell; forming conductive material in the second opening and directly against a top of the top electrode material that is in the first opening; and removing the conductive material from being atop the top electrode material that is in the first opening.

Assignees

• Micron Technology Inc

Inventors

• Sills Scott E

Classifications

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D1/716 Primary

  having vertical extensions · CPC title

• H10D1/692

  Electrodes · CPC title

• H10D1/042

  using deposition processes to form electrode extensions · CPC title

• H10B12/03 Primary

  Making the capacitor or connections thereto · CPC title