Discrete three-dimensional processor

Patent metadata

Field	Value
Publication number	US-11960987-B2
Application number	US-202318096013-A
Country	US
Kind code	B2
Filing date	Jan 12, 2023
Priority date	Dec 10, 2018
Publication date	Apr 16, 2024
Grant date	Apr 16, 2024

Abstract

A discrete three-dimensional (3-D) processor a plurality of storage-processing units (SPU's), each of which comprises a non-memory circuit and more than one 3-D memory (3D-M) array. The preferred 3-D processor further comprises communicatively coupled first and second dice. The first die comprises the 3D-M arrays and the in-die peripheral-circuit components thereof; whereas, the second die comprises the non-memory circuits and off-die peripheral-circuit components of the 3D-M arrays.

First claim

What is claimed is:

1. A discrete three-dimensional (3-D) processor, comprising:
a plurality of storage-processing units (SPU's), each of said SPU's comprising a non-memory circuit and more than one 3-D memory (3D-M) array;
a first die on a first semiconductor substrate, wherein said 3D-M array comprises memory cells stacked above said first semiconductor substrate, and an in-die peripheral-circuit component of said 3D-M array is disposed on said first semiconductor substrate;
a second die on a second semiconductor substrate, wherein at least a portion of said non-memory circuit and an off-die peripheral-circuit component of said 3D-M array are disposed on said second semiconductor substrate;
wherein, said non-memory circuit is not a part of a memory; said first die does not comprise said off-die peripheral-circuit component; said first and second dice are communicatively coupled by a plurality of inter-die connections; said first and second semiconductor substrates are separate semiconductor substrates.

2. The 3-D processor according to claim 1 , wherein:
each of said SPU's comprises at least four 3D-M arrays including said 3D-M arrays;
or, each of said SPU's comprises at least eight 3D-M arrays including said 3D-M arrays;
or, said 3D-M array comprises a plurality of vertically stacked memory cells without any semiconductor substrate therebetween; or,
said 3D-M array is a 3-D random-access memory (3D-RAM) array; or,
said 3D-M array is a 3-D read-only memory (3D-ROM) array; or,
said 3D-M array is a non-volatile memory (NVM) array; or,
said 3D-M array is a 3-D writable memory (3D-W) array; or,
said 3D-M array is a 3-D printed memory (3D-P) array; or
said 3D-M array is a horizontal 3D-M (3D-MH) array; or,
said 3D-M array is a vertical 3D-M (3D-Mv) array; or
said 3D-M array is a 3D-static random access memory (3D-SRAM), 3D-dynamic random access memory (3D-DRAM), 3D-resistive random access memory (3D-RRAM), 3D-magnetoresistive random access memory (3D-MRAM), or 3D-ferroelectric random access memory (3D-FeRAM) array; or,
said 3D-M array is a 3D-mask programmable read-only memory (3D-MPROM), 3D-one-time-programmable (3D-OTP), 3D-multi-time-programmable (3D-MTP), 3D-erasable programmable read-only memory (3D-EPROM), 3D-electrically erasable programmable read-only memory (3D-EEPROM), 3D-flash, 3D-NOR, 3D-NAND, or 3D-XPoint array.

3. The 3-D processor according to claim 2 , wherein:
a first number of the back-end-of-line (BEOL) layers of said first die is larger than a second number of the BEOL layers of said second die; or,
a third number of the address-line layers of said first die is at least twice as much as a fourth number of the interconnect layers of said second die; or,
a fifth number of the memory cells on each memory string in said first die is at least twice as much as a sixth number of the interconnect layers of said second die; or,
a seventh number of the interconnect layers in the substrate circuit of said first die is smaller than an eighth number of the interconnect layers of said second die; or,
the interconnect material used in said second die has a lower resistivity than the interconnect material used the substrate circuit of said first die.

4. The 3-D processor according to claim 3 , wherein:
said non-memory circuit is a logic circuit; or,
said non-memory circuit is a processing circuit; or,
said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model; said non-memory circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT; whereby said 3-D processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC; or,
said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function; said non-memory circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT); whereby said 3-D processor customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE; or,
said 3-D processor further comprises an input for transferring at least a first portion of a first pattern; said 3D-M array stores at least a second portion of a second pattern; said non-memory circuit comprises a pattern-processing circuit for performing pattern processing for said first and second patterns; or,
said 3-D processor is a discrete 3-D processor with embedded search-pattern library, further comprising an input for transferring at least a target pattern; said 3D-M array stores at least a search pattern; said non-memory circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3-D processor is a discrete 3-D storage with in-situ pattern-processing capabilities, further comprising an input for transferring at least a search pattern; said 3D-M array stores at least a target pattern; said non-memory circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern; or,
said 3D-M array stores at least a portion of a synaptic weight; said non-memory circuit comprises a neuro-processing circuit for performing neural processing with said synaptic weight.

5. The 3-D processor according to claim 3 , wherein:
said off-die peripheral-circuit component comprises at least a portion of an address decoder; or,
said off-die peripheral-circuit component comprises at least a portion of a sense amplifier; or,
said off-die peripheral-circuit component comprises at least a portion of a programming circuit; or,
said off-die peripheral-circuit component comprises at least a portion of a read-voltage generator; or,
said off-die peripheral-circuit component comprises at least a portion of a write-voltage generator; or,
said off-die peripheral-circuit component comprises at least a portion of a data buffer.

6. The 3-D processor according to claim 4 , wherein:
said off-die peripheral-circuit component comprises at least a portion of an address decoder; or,
said off-die peripheral-circuit component comprises at least a portion of a sense amplifier; or,
said off-die peripheral-circuit component comprises at least a portion of a programming circuit; or,
said off-die peripheral-circuit component comprises at least a portion of a read-voltage generator; or,
said off-die peripheral-circuit component comprises at least a portion of a write-voltage generator; or,
said off-die peripheral-circuit component comprises at least a portion of a data buffer.

7. The 3-D processor according to claim 3 , wherein:
said first and second dice are vertically stacked; or,
said first and second dice are face-to-face bonded; or,
said first and second dice have a same die size; or,
a first edge of said first die is aligned with a second edge of said second die; or,
the projection of said 3D-M array on said second die at least partially overlaps said non-memory circuit; or,
each 3D-M array is vertically aligned and communicatively coupled with a non-memory circuit; or,
each non-memory circuit is vertically aligned and communicatively coupled with at least a 3D-M array; or,
the pitch of said non-memory circuit is an integer multiple of the pitch of said 3D-M array; or,
said inter-die connections include bond wires, micro-bumps, through-silicon-vias (TSV's), and/or vertical interconnect access (VIA's).

8. The 3-D processor according to claim 7 , wherein:
said non-memory circuit is a logic circuit; or,
said non-m

Assignees

• Zhang Guobiao
• Hangzhou Haicun Information Tech Co Ltd

Inventors

• Zhang Guobiao

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W80/00

  Direct bonding of chips, wafers or substrates · CPC title

• H10W90/792

  between multiple chips · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title