Discrete three-dimensional vertical memory comprising off-die address/data-translator

Patent metadata

Field	Value
Publication number	US-9305604-B2
Application number	US-201514707023-A
Country	US
Kind code	B2
Filing date	May 8, 2015
Priority date	Sep 1, 2011
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

The present invention discloses a discrete three-dimensional vertical memory (3D-M V ). It comprises at least a 3D-array die and at least an A/D-translator die. The 3D-array die comprises a plurality of vertical memory strings. At least an address/data (A/D)-translator for the 3D-array die is located on the A/D-translator die instead of the 3D-array die. The 3D-array die and the A/D-translator die have substantially different back-end-of-line (BEOL) structures.

First claim

What is claimed is:

1. A discrete three-dimensional vertical memory (3D-M V ), comprising:
a 3D-array die comprising at least a 3D-M V array, wherein said 3D-M V array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells;
an A/D-translator die comprising at least a portion of an address/data-translator, wherein said portion of said address/data-translator is absent from said 3D-array die;
means for coupling said 3D-array die and said A/D-translator die;
wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is substantially more than the number of interconnect levels in said A/D-translator die; and, said 3D-array die and said A/D-translator die are separate dice.

2. The memory according to claim 1 , wherein said 3D-array die further comprises at least a peripheral circuit located outside said 3D-M V array, and the number of interconnect levels of said A/D-translator die is more than the number of interconnect levels of said peripheral circuit.

3. The memory according to claim 1 , wherein said 3D-array die further comprises at least a peripheral circuit located outside said 3D-M V array, and said peripheral circuit and said A/D-translator die comprise different interconnect materials.

4. The memory according to claim 1 , wherein said 3D-M V is a vertical-NAND.

5. The memory according to claim 1 , wherein each of said memory cells comprises at least a vertical transistor.

6. The memory according to claim 1 , wherein said 3D-M V is a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

7. The memory according to claim 1 , wherein said 3D-array die and said A/D-translator die are located in a memory package, a memory module, a memory card, or a solid-state drive.

8. The memory according to claim 1 , further comprising another 3D-array die including at least another 3D-M V array, wherein said A/D-translator die comprises at least another portion of another address/data-translator for said another 3D-array die.

9. The memory according to claim 1 , wherein said address/data-translator comprises at least an address translator and/or a data translator.

10. A discrete three-dimensional vertical memory (3D-M V ), comprising:
a 3D-array die comprising at least a 3D-M V array and a peripheral circuit located outside said 3D-M V array, wherein said 3D-M V array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells;
an A/D-translator die comprising at least a portion of an address/data-translator, wherein said portion of said address/data-translator is absent from said 3D-array die;
means for coupling said 3D-array die and said A/D-translator die;
wherein said peripheral circuit and said A/D-translator die comprise different interconnect materials; and, said 3D-array die and said A/D-translator die are separate dice.

11. The memory according to claim 10 , wherein said peripheral circuit comprises high-temperature interconnect materials.

12. The memory according to claim 10 , wherein said A/D-translator die comprises high-speed interconnect materials.

13. The memory according to claim 10 , wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is substantially more than the number of interconnect levels in said A/D-translator die.

14. The memory according to claim 10 , wherein the number of interconnect levels of said A/D-translator die is more than the number of interconnect levels of said peripheral circuit.

15. The memory according to claim 10 , wherein said 3D-M V is a vertical-NAND.

16. The memory according to claim 10 , wherein each of said memory cells comprises at least a vertical transistor.

17. The memory according to claim 10 , wherein said 3D-M V is a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

18. The memory according to claim 10 , wherein said 3D-array die and said A/D-translator die are located in a memory package, a memory module, a memory card, or a solid-state drive.

19. The memory according to claim 10 , further comprising another 3D-array die including at least another 3D-M V array, wherein said A/D-translator die comprises at least another portion of another address/data-translator for said another 3D-array die.

20. The memory according to claim 10 , wherein said address/data-translator comprises at least an address translator and/or a data translator.

Assignees

• Zhang Guobiao
• Hangzhou Haicun Information Technology Co Ltd

Inventors

• Zhang Guobiao

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title