Discrete three-dimensional vertical memory

Patent metadata

Field	Value
Publication number	US-9305605-B2
Application number	US-201514884760-A
Country	US
Kind code	B2
Filing date	Oct 15, 2015
Priority date	Sep 1, 2011
Publication date	Apr 5, 2016
Grant date	Apr 5, 2016

Abstract

The present invention discloses a discrete three-dimensional vertical memory (3D-M V ). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. At least an off-die peripheral-circuit component of the 3D-M V arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.

First claim

What is claimed is:

1. A discrete three-dimensional vertical memory (3D-M V ), comprising:
a 3D-array die comprising at least a 3D-M V array, wherein said 3D-M V array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells;
a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-M V array, wherein said off-die peripheral-circuit component is absent from said 3D-array die;
means for coupling said 3D-array die and said peripheral-circuit die;
wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is at least twice as much as the number of interconnect levels in said peripheral-circuit die; and, said 3D-array die and said peripheral-circuit die are separate dice.

2. The memory according to claim 1 , wherein said 3D-M V is a vertical-NAND, a three-dimensional read-only memory (3D-ROM), or a three-dimensional random-access memory (3D-RAM).

3. The memory according to claim 1 , wherein said 3D-array die and said peripheral-circuit die are located in a memory package, a memory module, a memory card, or a solid-state drive.

4. The memory according to claim 1 , further comprising another 3D-array die including at least another 3D-M V array, wherein said peripheral-circuit die comprises at least another portion of another off-die peripheral-circuit component for said another 3D-array die.

5. The memory according to claim 1 , wherein said off-die peripheral-circuit component is a read-voltage generator and/or a write-voltage generator.

6. The memory according to claim 1 , wherein said off-die peripheral-circuit component is an address translator and/or a data translator.

Assignees

• Chengdu Haicun Ip Technology Llc

Inventors

• Zhang Guobiao

Classifications

• G11C8/14

  Word line organisation; Word line lay-out · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title

• G11C5/145

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title